Managing Reconfigurable Instructions The end of Denard scaling has brought with it the end of performance improvements using traditional microprocess

管理可重配置指令 Denard 缩放的结束也带来了使用传统微处理的性能改进的结束

• 批准号: 2265128
• 金额: --
• 依托单位: University of Edinburgh
• 依托单位国家: 英国
• 项目类别: Studentship
• 财政年份: 2019
• 资助国家: 英国
• 起止时间: 2019 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=studentship-2265128
• 关键词: Managing; Reconfigurable; Instructions; end; Denard

One approach to addressing this problemis multi-core scaling, an approach neither absent of challengesnor expected to continue to help indefinitely.ASICs, which remove many of the overheads of traditional microprocessordesign, are another promising approach. However, thus far, ASIC-basedaccelerators exist only in specific domains, for example in NICscomputing packet check sequences or in FPGAs performingsimple math operations. The problem here is threefold:1. Selection of effective accelerators is challenging.2. Once hardened, an ASIC cannot be changed --- this compacts the difficulties above.3. Accelerators cannot all be close to the CPU, meaning that communication costs can be high.Reconfigurable hardware addresses these concerns.CGRAs are one approach to maintaining the performance benefits of ASICs and the flexibility of FPGAs. Selection of suitable hard-blocks is still a challenge,and mapping existing programs to CGRAs is difficult. The space of hardware accelerators is far greater than existing CGRAs,but more compiler work is neededto support CGRAs with a variety of hardware. Existing commercialsolutions, such as the Merlin compiler focus largely onoffloading computation to FPGAs and support a limited number offixed CGRA architectures. LegUp fulfills a similarrole, but targeting FPGAs. DSLs are also a typical way to program CGRAs but comewith steep learning curves and typically apply to a small numberof CGRAs. Existing techniques for mapping to devices withhard-blocks focus largely on fixed functionalitydevices. I propose targeting CGRAsfrom legacy code in the same way that these works targetfixed-function accelerators. More broadly, my workwill provide understanding about the tradeoffs between the broadapplicability of finely reconfigurable designs and the efficiencyof ASICs.An obvious question is: what is the best architecture to target?One approach to this question is: given some fixed-function ASIC, how can thecoverage of the accelerator be extended to a number of applications by introducing somereconfigurability? The compilerplays a key role in answering this question, because the problem of offloading functionalityfrom multiple applications becomes a task of mapping different applications toaccelerators that differ very slightly.But this is a chicken-and-egg problem: we need a technique to move from anASIC accelerator to an accelerator with a small amount of reconfigurability but muchbroader applicability before the appropriate compiler techniques can bedeveloped. But without the compiler techniques, the potential acceleratorcoverage benefits will be unknown.I propose the development of a tool that will address this problem. Given anASIC with an associated functional description and a set of applications, it willfind a reconfigurable accelerator with an appropriate amount of reconfigurability.There are several phases to this project:1. Identify a suitable functional description that captures both accelerator behaviour, and suitable opportunities for reconfigurability. There are a few languages that can be used to describe CGRAs that should also be used as a starting point, Toronto's CGRA-ME, Tubingen's CGADL and U Washington's SPR. This step largely requires thinking about what kinds of reconfigurability make sense, and understanding a few higher level description languages. Basically, I see this part as the ``get a human intuition for what I want to do''. 2. Find an efficient way to match this flexible accelerator to code to a code-base in a way where we minimise flexibility while maximising coverage. The idea of this one is to output a description with the ``right'' level of flexibility. 3. The last part is a pass that can match the partially-reconfigurable accelerator to some new code.

解决这个问题的一种方法是多核扩展，这种方法既不是没有挑战，也不会无限期地继续提供帮助。asic消除了传统微处理器设计的许多开销，是另一种有前途的方法。然而，到目前为止，基于asic的加速器只存在于特定的领域，例如在nic计算数据包检查序列或执行简单数学运算的fpga中。这里的问题有三个方面：1。选择有效的加速器是一项挑战。一旦硬化，ASIC就不能改变——这就简化了上述困难。加速器不可能都靠近CPU，这意味着通信成本可能很高。可重构硬件解决了这些问题。CGRAs是保持asic性能优势和fpga灵活性的一种方法。选择合适的硬块仍然是一个挑战，将现有的程序映射到CGRAs是困难的。硬件加速器的空间远远大于现有的CGRAs，但是需要更多的编译器工作来支持各种硬件的CGRAs。现有的商业解决方案，如Merlin编译器，主要集中在fpga上卸载计算，并支持有限数量的固定CGRA架构。LegUp扮演着类似的角色，但目标是fpga。dsl也是编程CGRAs的一种典型方法，但学习曲线陡峭，通常适用于少量CGRAs。现有的映射到带有硬块的设备的技术主要集中在固定功能的设备上。我建议用与固定函数加速器相同的方式从遗留代码中瞄准cgrasse。更广泛地说，我的工作将提供对精细可重构设计的广泛适用性和asic效率之间权衡的理解。一个显而易见的问题是：什么是最好的体系结构目标？解决这个问题的一种方法是：给定一些固定功能的ASIC，如何通过引入一些可配置性将加速器的覆盖范围扩展到许多应用程序？编译器在回答这个问题时扮演着关键的角色，因为从多个应用程序卸载功能的问题变成了将不同的应用程序映射到差别很小的加速器的任务。但这是一个先有鸡还是先有蛋的问题：在开发合适的编译器技术之前，我们需要一种技术将asic加速器转换为具有少量可重构性但更广泛适用性的加速器。但是如果没有编译器技术，潜在的加速器覆盖优势将是未知的。我建议开发一种工具来解决这个问题。给定一个具有相关功能描述和一组应用的asic，它将找到一个具有适当可重构性的可重构加速器。这个项目有几个阶段：1。确定一个合适的功能描述，它既可以捕获加速器行为，也可以捕获可重构性的合适机会。有一些语言可以用来描述CGRAs，也可以作为一个起点，多伦多的CGRA-ME，蒂宾根的CGADL和华盛顿的SPR。这一步很大程度上需要考虑什么类型的可重构性是有意义的，并理解一些更高级的描述语言。基本上，我认为这部分是“对我想做的事情有一个人类的直觉”。2. 找到一种有效的方法，将这种灵活的加速器与代码库相匹配，以最小化灵活性的同时最大化覆盖范围。这种方法的思想是输出具有“适当”灵活性的描述。3. 最后一部分是一个通道，它可以将部分可重构加速器与一些新代码相匹配。