High kinetic inductance thin films for compact readout of CMOS-compatible spin qubits

为了充分展示量子计算机相对于经典方法的优势，可用的量子比特数量必须显著增加，超过目前使用最先进超导量子比特的可行数量。自旋量子比特可以使用硅晶体管来实现，其制造方式与现代技术中用于制造芯片的cmos工艺兼容。通过使用这种成熟的硅技术，可以实现1010个量子比特/平方厘米的量子比特密度。然而，电流读出电路将该值降低到103量子比特/平方厘米，这阻碍了可扩展性，而可扩展性是与CMOS兼容的方法的主要优点。为了解决这一问题，可以采用高动态电感(KI)材料作为栅电极，既可以限制电子，又可以作为读出的谐振器。这将减小读出电路的尺寸，因为由于KI，可以在较小的区域中实现高电感。为了实现这一目标，首先需要研究多种高KI材料，以确定它们的适用性。对于制造的谐振器，材料必须表现出低损耗和相应的高Q因数，因为这决定了对用于读出量子比特态的电容漂移的敏感性。同样重要的是它们对操纵自旋量子比特所需的磁场(对于单重态-三重态为_1T，对于其他实现为_1.5T)的弹性。然后，将设计、制造和测试包括所选高KI材料作为栅电极的量子点器件。对这些器件的了解将有助于开发具有多个栅极的纳米线，以通过制造4量子位单元来展示这种方法的可扩展性。

For quantum computers to fully demonstrate their advantage over classical approaches, the number of qubits available must significantly increase beyond that currently feasible using state of the art superconducting qubits. Spin qubits can be realised using silicon transistors fabricated in a way that is compatible with the CMOS processes used to manufacture chips found in modern technologies. Through the use of this mature silicon technology a qubit density of 1010 qubits/cm2 could be possible. However, the current readout circuitry reduces this value to 103 qubits/cm2 hindering the scalability that is the main benefit of a CMOS-compatible approach. To solve this issue, a high kinetic inductance (KI) material can be incorporated as the gate electrode to both confine electrons and act as the resonator for readout. This will reduce the size of the readout circuitry as a high inductance can be achieved in a smaller area due to the KI. To achieve this goal first involves investigating multiple high KI materials to determine their applicability. The material must demonstrate low loss and correspondingly high Q-factors for fabricated resonators as this determines the sensitivity to capacitance shifts used to readout the qubit state. Also of importance is their resilience to magnetic fields (_1T for singlet-triplet and _1.5T for other implementations) which are needed for manipulation of the spin qubits. Quantum dot devices that include the chosen high KI material as the gate electrode will then be designed, fabricated and tested. An understanding of these devices will allow the development of a nanowire with multiple gates to demonstrate the scalability of this approach with the fabrication of a 4-qubit unit cell.