DSP Architecture: efficiency of accelerators in high throughput computations

DSP 架构：高吞吐量计算中加速器的效率

• 批准号: 2590731
• 金额: --
• 依托单位: University of Edinburgh
• 依托单位国家: 英国
• 项目类别: Studentship
• 财政年份: 2022
• 资助国家: 英国
• 起止时间: 2022 至 无数据
• 项目状态: 未结题
• 来源: https://gtr.ukri.org/projects?ref=studentship-2590731
• 关键词: DSP; Architecture; efficiency; accelerators; throughput

The main idea of this research is to develop new Digital Signal Processor (DSP)architectures for the efficient control of embedded accelerators.It can be difficult to define what embedded systems are, but a characteristicfeature is that they are not general purpose systems, but are systems which aredesigned to perform a specific set of tasks.Previous work in this area has not addressed the challenges of real-time manythreaded architectures, including the key task of coordinating large number ofstreaming accelerators.Also, simultaneous multithreading technology has so far not been used inembedded systems, mainly because embedded systems tend to require real-timedeterminism.This proposal aims to answer the following questions:- Can computations be performed more efficiently in software defined radioapplications?- Can task scheduling of multithreaded systems be made more deterministic forreal-time control applications?The fundamental challenges to be addressed by this proposed research are:- How to optimize DSP architectures to support real-time control of embeddedaccelerators, with reference to applications such asSoftware Defined Radio (SDR);- In high-throughput computation, involving real-time DSP architectures, how canfrequently used DSP tasks be offloaded to accelerators in the most efficientway;- Can the DSP processor be rearchitected to support other types ofhigh-throughput numerical computations such as deep learning;- Would expanding the instruction set of a generic processor with DSP/SDRspecific instructions give similar performance gains;- The implementation and control of accelerator blocks within a potentiallymultithreaded design and achieving more determinism within multithreadedembedded processorsFundamentally, the unifying question is: can digital signal processors be madefaster, more efficient and be utilized in more varied applications?

本研究的主要思想是开发新的数字信号处理器（DSP）架构，以有效地控制嵌入式加速器。很难定义什么是嵌入式系统，但一个典型的特征是，它们不是通用系统，而是被设计来执行一组特定任务的系统。在这一领域的以前的工作还没有解决实时多线程架构的挑战，包括协调大量流加速器的关键任务。此外，同时多线程技术到目前为止还没有在嵌入式系统中使用，主要是因为嵌入式系统往往需要实时确定性。该建议旨在回答以下问题：-在软件定义的无线电应用中，计算是否可以更有效地执行？-多线程系统的任务调度是否能使实时控制应用程序的确定性更强？本研究提出的基本挑战是：-如何优化DSP架构以支持嵌入式加速器的实时控制，参考软件定义无线电（SDR）等应用;-在涉及实时DSP架构的高吞吐量计算中，如何以最有效的方式将频繁使用的DSP任务卸载到加速器;-DSP处理器是否可以重新架构以支持其他类型的高吞吐量数值计算，如深度学习;- 将DSP/SDR特定指令扩展到通用处理器的指令集是否会带来类似的性能增益;-在潜在的多线程设计中实现和控制加速器块，并在多线程嵌入式处理器中实现更多的确定性从根本上讲，统一的问题是：数字信号处理器能否更快、更高效，并用于更多样化的应用？