DSP Architecture: efficiency of accelerators in high throughput computations

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The main idea of this research is to develop new Digital Signal Processor (DSP)architectures for the efficient control of embedded accelerators.It can be difficult to define what embedded systems are, but a characteristicfeature is that they are not general purpose systems, but are systems which aredesigned to perform a specific set of tasks.Previous work in this area has not addressed the challenges of real-time manythreaded architectures, including the key task of coordinating large number ofstreaming accelerators.Also, simultaneous multithreading technology has so far not been used inembedded systems, mainly because embedded systems tend to require real-timedeterminism.This proposal aims to answer the following questions:- Can computations be performed more efficiently in software defined radioapplications?- Can task scheduling of multithreaded systems be made more deterministic forreal-time control applications?The fundamental challenges to be addressed by this proposed research are:- How to optimize DSP architectures to support real-time control of embeddedaccelerators, with reference to applications such asSoftware Defined Radio (SDR);- In high-throughput computation, involving real-time DSP architectures, how canfrequently used DSP tasks be offloaded to accelerators in the most efficientway;- Can the DSP processor be rearchitected to support other types ofhigh-throughput numerical computations such as deep learning;- Would expanding the instruction set of a generic processor with DSP/SDRspecific instructions give similar performance gains;- The implementation and control of accelerator blocks within a potentiallymultithreaded design and achieving more determinism within multithreadedembedded processorsFundamentally, the unifying question is: can digital signal processors be madefaster, more efficient and be utilized in more varied applications?