Electronic Nervous Systems on Chip

技术扩展通过高密度集成组件和核心，以及提供片上系统(SoC)，例如NVIDIA Jetson、Xilinx UltraScale+FPGA、ARM Big.LITTLE，使计算体系结构得以快速发展。然而，随着时钟速度达到限制，此类系统正变得越来越热门，更容易出现故障和时序冲突。因此，部分SoC必须关闭以保持在热极限内(“暗硅”)。这将挑战从使设计变得更小，将新的重点放在超低功耗、弹性和自主适应异常、故障、时序违规和性能下降的系统上。由辐射引起的暂时性故障和由于制造缺陷和应力引起的永久性故障的数量几乎呈指数增长。ITRS(https://irds.ieee.org/)估计短期内显著的设备故障率，例如由于磨损。因此，对这样的系统的一个关键要求是在运行时有效地执行检测和分析，并且在最小的面积和功率开销内。这与当前最先进的技术水平不一致，包括纠错码(ECC)、内建自测试(BIST)、局部故障检测和传统的模块冗余策略(TMR)，所有这些都导致高得令人望而却步的系统开销，无法适应、定位或预测故障。在复杂的生物有机体中，神经系统是一个更有效和更适应的“子系统”，它通过在有机体的不同部分之间传输信号来检测环境变化和影响它们的异常。神经系统与内分泌系统协同工作，触发适当的调节或修复反应。神经系统自然地放大、适应，并以非中心化的方式自主运行。在片上神经系统项目中，总体愿景是振兴现代电子系统，特别是这些系统被设计为自主行为的方式，以变得更可靠。该项目的目标是开发一种方法，用于具有嵌入人工神经系统的“自我感知”电子系统，可以感知其状态和性能，并利用这些生物启发机制的结构和计算能力来自主容错。芯片上的神经系统是一种跨学科的合作，它将具有电子系统的尖峰神经元网络聚集在一起，以便它们形成具有内在嵌入的人工“神经系统”的硬件平台。这种方法以前从未被用来使我们口袋里随身携带的技术更高效、更可靠，使这项研究在仿生电子系统设计的前沿“蓝天”。为了确保可行性，这项研究建立在一些日益复杂的硬件演示基础上。NeXY正在使用最先进的UltraScale+FPGA进行神经系统组件的快速原型制作，并与电子设计环境相辅相成，开发这一领域的模型和方法将是该博士项目的重点。为了确保项目之外的可访问性，将开发设计方法和EDA工具，支持电子神经系统组件与传统电路设计的自动集成和培训，使工程师能够应用我们的技术，而不必担心电子-神经元接口的复杂细节。作为更广泛研究项目的一部分，我们将与Xilinx合作，在HDL级数字FPGA设计中演示这一点。为了确保可扩展性，我们将在我们的合作伙伴ARM提供的一系列相关大规模处理器设计上验证和评估片上神经系统方法，ARM也将就故障性能要求提供建议。

Technology scaling has enabled fast advancement of computing architectures through high-density integration of components and cores, and the provision of systems on chip (SoC), e.g. NVIDIA Jetson, Xilinx UltraScale+ FPGA, ARM big.LITTLE. However, such systems are becoming hot and more prone to failure and timing violations as clock speed limits are reached. Therefore, parts of SoCs must be turned off to stay within thermal limits ("dark silicon"). This shifts challenges away from making designs smaller, setting the new focus on systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies, faults, timing violations and performance degradation. There is a near exponential increase in the numbers of temporary faults caused by radiation, and permanent faults due to manufacturing defects and stress. ITRS (https://irds.ieee.org/) estimates significant device failure rates, e.g. due to wear-out, in the short term. Hence, a critical requirement for such systems is to effectively perform detection and analysis at runtime, within a minimal area and power overhead. This is at odds with current state-of-the-art, including error correcting codes (ECC), built-in-self-test (BIST), localized fault detection, and traditional modular redundancy strategies (TMR), all resulting in prohibitively high system overheads and an inability to adapt, locate or predict faults.In complex living organisms, the nervous system is a much more efficient and adaptive "subsystem" that detects environmental changes and anomalies that impact them by transmitting signals between different parts of the organism. The nervous system works in tandem with the endocrine system, triggering appropriate regulatory or repair responses. Nervous systems naturally scale up, adapt and operate autonomously in a de-centralised manner. In the Nervous Systems on Chip project the overall vision is to rejuvenate modern electronic systems and particularly the way in which such systems are designed to act autonomously to become more reliable.The goal of the project is to develop a methodology for "self-aware" electronic systems with an embedded artificial nervous system that can sense its state and performance, and exploit the structure and computational power of these kinds of bio-inspired mechanisms for autonomous tolerance of faults. Nervous Systems on Chip is an inter-disciplinary collaboration that brings together networks of spiking neurons with electronic systems, so that they form hardware platforms with inherently embedded artificial "nervous systems". This approach has never before been used to make the technology we all carry around in our pockets more efficient and reliable, making the research "blue-skies" at the cutting edge of bio-inspired electronic systems design.To ensure feasibility, the research is built around a number of hardware demonstrators of increasing complexity. NERVOUS is making use of state-of-the-art UltraScale+ FPGAs for rapid prototyping of nervous system components and complementing with an electronic design environment and developing models and methodologies in this area will be a focus of this PhD project.To ensure accessibility beyond the project, a design methodology will be developed and an EDA tool supporting automatic integration and training of electronic nervous system components with traditional circuit designs, allowing engineers to apply our technology without having to worry about the intricate details of electronic-neuron interfacing. This will be demonstrated for digital FPGA designs at the HDL level in collaboration with Xilinx as part of the wider research project.To ensure scalability, we will verify and evaluate the Nervous Systems on Chip methodology on a range of relevant large-scale processor designs provided by our partner ARM, who will also advise on fault performance requirements.