Electronic Nervous Systems on Chip

通过组件和核心的高密度集成，以及提供片上系统（SoC），例如NVIDIA Jetson， Xilinx UltraScale+ FPGA, ARM big.LITTLE，技术扩展实现了计算架构的快速发展。然而，这样的系统正变得越来越热，并且随着时钟速度限制的达到，更容易出现故障和时间违规。因此，soc的某些部分必须关闭以保持在热限制内（“暗硅”）。这将挑战从小型化设计转移到超低功耗、弹性和自主适应异常、故障、定时违规和性能下降的系统上。由辐射引起的临时故障和由制造缺陷和应力引起的永久故障的数量几乎呈指数增长。ITRS （https://irds.ieee.org/）估计短期内显著的设备故障率，例如由于磨损。因此，这种系统的一个关键要求是在运行时有效地执行检测和分析，在最小的面积和功率开销内。这与当前最先进的技术不一致，包括纠错码（ECC）、内置自检（BIST）、局部故障检测和传统的模块化冗余策略（TMR），所有这些都会导致过高的系统开销，并且无法适应、定位或预测故障。在复杂的生物体中，神经系统是一个效率更高、适应性更强的“子系统”，它通过在生物体的不同部分之间传递信号来检测影响它们的环境变化和异常。神经系统与内分泌系统协同工作，触发适当的调节或修复反应。神经系统自然地以去中心化的方式扩大、适应和自主运作。在芯片上的神经系统项目中，总体愿景是使现代电子系统恢复活力，特别是使这些系统能够自主行动，从而变得更加可靠。该项目的目标是开发一种“自我意识”电子系统的方法，该系统具有嵌入式人工神经系统，可以感知其状态和性能，并利用这些类型的生物启发机制的结构和计算能力来自主容错。芯片上的神经系统是一项跨学科合作，它将脉冲神经元网络与电子系统结合在一起，从而形成具有内在嵌入式人工“神经系统”的硬件平台。这种方法以前从未被用于使我们随身携带的技术更加高效和可靠，使研究在生物启发电子系统设计的前沿成为“蓝天”。为了确保可行性，该研究是围绕一些日益复杂的硬件演示构建的。NERVOUS正在利用最先进的UltraScale+ fpga快速制作神经系统组件的原型，并与电子设计环境相辅相成，开发该领域的模型和方法将是该博士项目的重点。为了确保项目之外的可访问性，将开发一种设计方法和一种EDA工具，支持电子神经系统组件与传统电路设计的自动集成和培训，使工程师能够应用我们的技术，而不必担心电子神经元接口的复杂细节。作为更广泛的研究项目的一部分，这将与赛灵思合作，在HDL级别的数字FPGA设计中进行演示。为了确保可扩展性，我们将在我们的合作伙伴ARM提供的一系列相关大型处理器设计上验证和评估神经系统芯片方法，ARM还将提供故障性能要求方面的建议。

Technology scaling has enabled fast advancement of computing architectures through high-density integration of components and cores, and the provision of systems on chip (SoC), e.g. NVIDIA Jetson, Xilinx UltraScale+ FPGA, ARM big.LITTLE. However, such systems are becoming hot and more prone to failure and timing violations as clock speed limits are reached. Therefore, parts of SoCs must be turned off to stay within thermal limits ("dark silicon"). This shifts challenges away from making designs smaller, setting the new focus on systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies, faults, timing violations and performance degradation. There is a near exponential increase in the numbers of temporary faults caused by radiation, and permanent faults due to manufacturing defects and stress. ITRS (https://irds.ieee.org/) estimates significant device failure rates, e.g. due to wear-out, in the short term. Hence, a critical requirement for such systems is to effectively perform detection and analysis at runtime, within a minimal area and power overhead. This is at odds with current state-of-the-art, including error correcting codes (ECC), built-in-self-test (BIST), localized fault detection, and traditional modular redundancy strategies (TMR), all resulting in prohibitively high system overheads and an inability to adapt, locate or predict faults.In complex living organisms, the nervous system is a much more efficient and adaptive "subsystem" that detects environmental changes and anomalies that impact them by transmitting signals between different parts of the organism. The nervous system works in tandem with the endocrine system, triggering appropriate regulatory or repair responses. Nervous systems naturally scale up, adapt and operate autonomously in a de-centralised manner. In the Nervous Systems on Chip project the overall vision is to rejuvenate modern electronic systems and particularly the way in which such systems are designed to act autonomously to become more reliable.The goal of the project is to develop a methodology for "self-aware" electronic systems with an embedded artificial nervous system that can sense its state and performance, and exploit the structure and computational power of these kinds of bio-inspired mechanisms for autonomous tolerance of faults. Nervous Systems on Chip is an inter-disciplinary collaboration that brings together networks of spiking neurons with electronic systems, so that they form hardware platforms with inherently embedded artificial "nervous systems". This approach has never before been used to make the technology we all carry around in our pockets more efficient and reliable, making the research "blue-skies" at the cutting edge of bio-inspired electronic systems design.To ensure feasibility, the research is built around a number of hardware demonstrators of increasing complexity. NERVOUS is making use of state-of-the-art UltraScale+ FPGAs for rapid prototyping of nervous system components and complementing with an electronic design environment and developing models and methodologies in this area will be a focus of this PhD project.To ensure accessibility beyond the project, a design methodology will be developed and an EDA tool supporting automatic integration and training of electronic nervous system components with traditional circuit designs, allowing engineers to apply our technology without having to worry about the intricate details of electronic-neuron interfacing. This will be demonstrated for digital FPGA designs at the HDL level in collaboration with Xilinx as part of the wider research project.To ensure scalability, we will verify and evaluate the Nervous Systems on Chip methodology on a range of relevant large-scale processor designs provided by our partner ARM, who will also advise on fault performance requirements.