Automating ISA support for Design Space Exploration

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Simulating ISAs for both architectural design and performance analysis provides a platform to help design a near-optimal processor for a given set of available technology, but this task is not trivial. Significant work is currently required to provide support for several architectures such as the recently supported RISC-VISA, one that I found promising but not yet mature enough for wide spread adoption through my research at the JSC. Automating this process would allow for a significant number of new architectures to be supported once released via Sail, a language that can provide the execution logic for a given processor[1]. This opens the door for future work of benchmarking, optimising and comparing several modern architectures without the error-prone work of adding support manually.