Hybrid CMOS-RRAM ANN accelerator chip

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The objective of the project is to design, build and benchmark a general-purpose ANN accelerator using a mixture of traditional CMOS and emerging RRAM technologies. The lynchpin of the idea is a minimalistic system consisting of 3x key blocks that perform signal processing across domains: an input processor converting a digital input into the time domain (D-T), a RRAM synapse converting a time-domain input into analogue output (T-A) and a very basic ADC-like "neuron" that converts analogue inputs to digital values (A-D). The latter can be then broadcast across the network and directly feed the input of the system. The advantage of this approach is that every operation is performed in its own, optimal domain whilst the circuits involved are all extremely minimalistic in implementation and perform the transformations "naturally", much like a resistor naturally converts a current passed through it into a voltage across its terminals. The system is conceived to attack the niche of low power, small size non-speed-critical systems.The project will require development of each of the basic circuits (input, synapse, neuron), along with an appropriate control and timing structure to orchestrate the operation of the system. Upgrades to be pursued during the project include a learning module. The final deliverable of the project would be a chip with RRAM devices post-processed on top of it, operating a simple ANN. This is likely to be a basic MNIST classification multi-layer perceptron with a basic CNN for image recognition to be pursued afterwards.