Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
批准号:
2404874
负责人:
Kai Ni
金额:
$24.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2023
资助国家:
美国
项目状态:
未结题
起止时间:
2023-10-01 至 2026-09-30
中文摘要
在人工智能的新时代,现代计算电子学面临着巨大的挑战,大量的计算任务,如机器人、AR/VR、自动驾驶,需要庞大的计算模型和巨大的计算工作量的支持。这样的需求使现有电子硬件的能力相形见绌。随着CMOS技术接近1nm节点,传统技术的扩展将很快失去动力,无法满足日益增长的计算能力需求。为了延续摩尔定律,基于HfO2的铁电场效应晶体管(FeFET)具有无挥发性、高能效和与CMOS兼容的优点,是领先的候选者之一。虽然许多器件级的开发已经在ffet上进行,但阻碍因素之一是器件的开发通常是在小范围内进行的,没有与CMOS技术的高级集成,这是提供完整的集成电路(IC)解决方案以支持现代计算任务所必需的。为了克服现有发展的限制,本提案将开发从器件到电路和架构的跨层技术,使极具前景的ffet器件与标准CMOS技术大规模集成。该项目将执行从器件到架构的全栈开发,以集成CMOS和ffet技术,针对新兴计算应用。在先进的技术节点上大规模地用CMOS制造ffet来演示所提出的技术。更具体地说,我们将执行以下开发。在器件级,将开发改进的非场效应管、pFeFET和CMOS之间集成的工艺,使ffet和CMOS器件更好地融合技术;在设计方法上,将开发一个联合器件-电路协同设计流程,以定制ffet技术,以满足人工智能等新兴计算应用的需求;此外,将开发利用ffet作为存储和计算器件的新型电路和架构,以利用ffet的特性及其与CMOS技术的共存;最后,将展示用于新兴应用的复杂处理器和加速器,结合CMOS和ffet技术,以展示与CMOS集成的新兴器件的优势。CMOS和ffet融合的集成方法和演示将体现ffet器件的系统视角,并为未来ffet的发展,特别是新兴的计算任务奠定坚实的基础。通过将先进的半导体技术与新兴的计算任务相结合,建议的项目为学生提供了强大的教育材料和机会,让他们了解现代计算技术和微电子器件的多学科发展。将开发前沿半导体和计算技术的课程材料和研讨会,为社会提供坚实的培训,同时促进大学STEM教育的多样性和包容性。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
In the new era of AI, modern computing electronics are facing tremendous challenges when a large amount of computing tasks, e.g. robotics, AR/VR, autonomous driving, require supports of gigantic computing models and enormous computing workloads. Such demands have dwarfed the capabilities of existing electronic hardware. As CMOS technology approaches 1 nm node, it is obvious that the conventional technology scaling will soon run out of steam to meet the ever-growing demand of computing power. To continue the Moore’s law, HfO2 based ferroelectric field effect transistor (FeFET) is one of the leading candidates with benefits of combined nonvolatility, high energy efficiency, and compatibility with CMOS. While many device-level developments have been performed on FeFET, one of the hindering factors is that the device’s development is often performed at small scale without high-level integration with CMOS technology, which is necessary to deliver a complete integrated-circuit (IC) solution for supporting the modern computing tasks. To overcome the limitation of existing developments, this proposal will develop cross-layer techniques from device to circuit and architecture enabling large-scale integration of the highly promising FeFET device with standard CMOS technology. This project will perform full-stack developments from device to architecture for the integration of CMOS and FeFET technology targeting emerging computing applications. Fabricated FeFET with CMOS at advanced technology nodes at a large scale will be used to demonstrate the proposed techniques. More specifically, we will perform the following developments. At device level, improved process for integration between nFeFET, pFeFET and CMOS will be developed allowing better technology fusion of the FeFET and CMOS devices; At design methodology, a joint device-circuit collaborative design flow will be developed to tailor the FeFET technology towards the need of emerging computing applications such as AI; Furthermore, novel circuit and architecture utilizing FeFET as both memory and computing devices will be developed to exploit the features of FeFET and its co-existence with CMOS technology; Finally, demonstrations on complex processors and accelerators for emerging applications, with joint CMOS and FeFET technology will be delivered to showcase the benefits of the emerging device integrated with CMOS. The integrative approach and demonstration of CMOS and FeFET fusion will manifest the system perspective of FeFET devices and establish a solid foundation for the future FeFET developments especially for the emerging computing tasks. By integrating the advanced semiconductor technology with emerging computing tasks, the proposed projects provide strong educational materials and opportunities for students to learn the multi-disciplinary developments of modern computing techniques and microelectronic devices. Both course materials and workshops on frontier semiconductor and computing techniques will be developed to provide solid training to the society while also promoting diversity and inclusion to college STEM education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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会议论文
Collaborative Research: FET: Medium:Compact and Energy-Efficient Compute-in-Memory Accelerator for Deep Learning Leveraging Ferroelectric Vertical NAND Memory
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批准号:2312884
-
项目类别:Standard Grant
-
资助金额:$26.8万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications
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批准号:2347024
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项目类别:Standard Grant
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资助金额:$42.82万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: FET: Medium:Compact and Energy-Efficient Compute-in-Memory Accelerator for Deep Learning Leveraging Ferroelectric Vertical NAND Memory
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批准号:2344819
-
项目类别:Standard Grant
-
资助金额:$26.8万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
CAREER: High-Performance Ferroelectric Memory for In-Memory Computing
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批准号:2239284
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项目类别:Continuing Grant
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资助金额:$54.99万
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财政年份:2023
-
负责人:Kai Ni
-
依托单位:
CAREER: High-Performance Ferroelectric Memory for In-Memory Computing
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批准号:2346953
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项目类别:Continuing Grant
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资助金额:$54.99万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
-
批准号:2318808
-
项目类别:Standard Grant
-
资助金额:$24.0万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications
-
批准号:2212240
-
项目类别:Standard Grant
-
资助金额:$42.82万
-
财政年份:2022
-
负责人:Kai Ni
-
依托单位:
国内基金
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