Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
批准号:
2404874
负责人:
Kai Ni
金额:
$24.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2023
资助国家:
美国
项目状态:
未结题
起止时间:
2023-10-01 至 2026-09-30
中文摘要
在人工智能的新时代,当机器人、AR/VR、自动驾驶等大量计算任务需要支持巨大的计算模型和巨大的计算工作量时,现代计算电子设备面临着巨大的挑战。这样的需求使现有电子硬件的能力相形见绌。随着CMOS技术接近1 nm节点,很明显,传统的技术扩展很快就会失去动力,以满足日益增长的计算能力需求。根据摩尔定律,基于HfO2的铁电场效应晶体管(FeFET)具有非易失性、高能效和与CMOS兼容等优点,是最有潜力的候选器件之一。虽然已经对FeFET进行了许多器件级的开发,但阻碍该器件开发的因素之一是,该器件的开发通常是在小范围内进行的,没有与CMOS工艺的高级别集成,这对于提供支持现代计算任务的完整集成电路(IC)解决方案是必要的。为了克服现有开发的局限性,该提案将开发从器件到电路和架构的跨层技术,从而实现前景广阔的FeFET器件与标准CMOS工艺的大规模集成。该项目将执行从设备到架构的全栈开发,以整合针对新兴计算应用的CMOS和FeFET技术。在先进的工艺节点上,我们将使用大规模的带有CMOS的制造的FeFET来演示所提出的技术。更具体地说,我们将进行以下发展。在器件层面,将开发改进的nFeFET、pFeFET和CMOS之间的集成工艺,使FeFET和CMOS器件实现更好的技术融合;在设计方法上,将制定联合器件-电路协同设计流程,以使FeFET技术适应人工智能等新兴计算应用的需求;此外,将开发利用FeFET作为存储器和计算器件的新型电路和架构,以利用FeFET的特性及其与CMOS技术的共存;最后,将展示适用于新兴应用的复杂处理器和加速器的演示,结合CMOS和FeFET技术,展示新兴器件与CMOS集成的好处。这一融合的方法和示范将体现FeFET器件的系统观点,并为未来的FeFET发展,特别是为新兴的计算任务奠定坚实的基础。通过将先进的半导体技术与新兴的计算任务相结合,建议的项目为学生提供了强大的教育材料和机会,让他们学习现代计算技术和微电子设备的多学科发展。将开发前沿半导体和计算技术的课程材料和研讨会,为社会提供坚实的培训,同时促进大学STEM教育的多样性和包容性。该奖项反映了NSF的法定使命,并通过使用基金会的智力优势和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
In the new era of AI, modern computing electronics are facing tremendous challenges when a large amount of computing tasks, e.g. robotics, AR/VR, autonomous driving, require supports of gigantic computing models and enormous computing workloads. Such demands have dwarfed the capabilities of existing electronic hardware. As CMOS technology approaches 1 nm node, it is obvious that the conventional technology scaling will soon run out of steam to meet the ever-growing demand of computing power. To continue the Moore’s law, HfO2 based ferroelectric field effect transistor (FeFET) is one of the leading candidates with benefits of combined nonvolatility, high energy efficiency, and compatibility with CMOS. While many device-level developments have been performed on FeFET, one of the hindering factors is that the device’s development is often performed at small scale without high-level integration with CMOS technology, which is necessary to deliver a complete integrated-circuit (IC) solution for supporting the modern computing tasks. To overcome the limitation of existing developments, this proposal will develop cross-layer techniques from device to circuit and architecture enabling large-scale integration of the highly promising FeFET device with standard CMOS technology. This project will perform full-stack developments from device to architecture for the integration of CMOS and FeFET technology targeting emerging computing applications. Fabricated FeFET with CMOS at advanced technology nodes at a large scale will be used to demonstrate the proposed techniques. More specifically, we will perform the following developments. At device level, improved process for integration between nFeFET, pFeFET and CMOS will be developed allowing better technology fusion of the FeFET and CMOS devices; At design methodology, a joint device-circuit collaborative design flow will be developed to tailor the FeFET technology towards the need of emerging computing applications such as AI; Furthermore, novel circuit and architecture utilizing FeFET as both memory and computing devices will be developed to exploit the features of FeFET and its co-existence with CMOS technology; Finally, demonstrations on complex processors and accelerators for emerging applications, with joint CMOS and FeFET technology will be delivered to showcase the benefits of the emerging device integrated with CMOS. The integrative approach and demonstration of CMOS and FeFET fusion will manifest the system perspective of FeFET devices and establish a solid foundation for the future FeFET developments especially for the emerging computing tasks. By integrating the advanced semiconductor technology with emerging computing tasks, the proposed projects provide strong educational materials and opportunities for students to learn the multi-disciplinary developments of modern computing techniques and microelectronic devices. Both course materials and workshops on frontier semiconductor and computing techniques will be developed to provide solid training to the society while also promoting diversity and inclusion to college STEM education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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会议论文
Collaborative Research: FET: Medium:Compact and Energy-Efficient Compute-in-Memory Accelerator for Deep Learning Leveraging Ferroelectric Vertical NAND Memory
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批准号:2312884
-
项目类别:Standard Grant
-
资助金额:$26.8万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications
-
批准号:2347024
-
项目类别:Standard Grant
-
资助金额:$42.82万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: FET: Medium:Compact and Energy-Efficient Compute-in-Memory Accelerator for Deep Learning Leveraging Ferroelectric Vertical NAND Memory
-
批准号:2344819
-
项目类别:Standard Grant
-
资助金额:$26.8万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
CAREER: High-Performance Ferroelectric Memory for In-Memory Computing
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批准号:2346953
-
项目类别:Continuing Grant
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资助金额:$54.99万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
CAREER: High-Performance Ferroelectric Memory for In-Memory Computing
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批准号:2239284
-
项目类别:Continuing Grant
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资助金额:$54.99万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications
-
批准号:2318808
-
项目类别:Standard Grant
-
资助金额:$24.0万
-
财政年份:2023
-
负责人:Kai Ni
-
依托单位:
Collaborative Research: SHF: Medium: A Comprehensive Modeling Framework for Cross-Layer Benchmarking of In-Memory Computing Fabrics: From Devices to Applications
-
批准号:2212240
-
项目类别:Standard Grant
-
资助金额:$42.82万
-
财政年份:2022
-
负责人:Kai Ni
-
依托单位:
国内基金
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