The Reduceron: high level symbolic computing on FPGA

Reduceron：FPGA 上的高级符号计算

• 批准号: EP/G011052/1
• 负责人: Colin Runciman
• 金额: $ 12.79万
• 依托单位: University of York
• 依托单位国家: 英国
• 项目类别: Research Grant
• 财政年份: 2008
• 资助国家: 英国
• 起止时间: 2008 至 无数据
• 项目状态: 已结题
• 来源: https://gtr.ukri.org/projects?ref=EP%2FG011052%2F1
• 关键词: Reduceron; level; symbolic; computing; FPGA

Symbolic computing is a key technology with programs often written in very expressive high level languages. The Reduceron is a custom processor for executing such symbolic programs by a technique called graph reduction. It is built on an FPGA (Field-Programmable Gate Array), a medium that allows rapid exploration of alternative designs. The current prototype was developed in just 2--3 months as a case-study in the closing stages of a PhD. Early results are sufficiently promising that we propose a 15-month feasibility study researching the potential of a special-purpose processor based on an advanced Reduceron. Results will be immediately applicable in FPGA-based systems and could inform the future design of a SPU (Symbolic Processing Unit) analogous to current highly successful GPUs for graphics.

符号计算是一项关键技术，通常用非常有表现力的高级语言编写程序。Reduceron是一个定制的处理器，通过一种称为图约简的技术来执行这种符号程序。它建立在FPGA（现场可编程门阵列）上，这是一种允许快速探索替代设计的介质。目前的原型仅用了2- 3个月的时间就开发出来，作为博士学位最后阶段的案例研究。早期的结果很有希望，我们提出了一个为期15个月的可行性研究，研究基于先进的Reduceron的专用处理器的潜力。结果将立即适用于基于fpga的系统，并可以为SPU（符号处理单元）的未来设计提供信息，类似于当前非常成功的图形gpu。

项目成果

The reduceron reconfigured

重新配置了reducer

• DOI: 10.1145/1932681.1863556
• 发表时间: 2010
• 期刊: ACM SIGPLAN Notices
• 作者: Naylor M

Supercompilation and the Reduceron

超级编译和Reducer

• 发表时间: 2010
• 作者: J Reich

Improvements to the design and description of the Reduceron

改进了Reducer的设计和描述

• 发表时间: 2009
• 作者: M Naylor