Methods for improving the physical optimization of asics structured asics and fpgas

现代集成电路设计者面临着许多问题：（1）电路很大，需要可扩展的算法;（2）不同的设计风格，包括ASIC，结构化ASIC和FPGA;（3）设计有多个目标，包括线长，可布线性和时序。布局仍然是物理设计中的关键步骤;它消耗大量的运行时间，并在很大程度上决定了整体互连。近几年来，就业安置在研究活动中得到了复兴。 本提案的目的是改进ASIC、结构化ASIC和FPGA设计风格的最新布局技术。ASIC和结构化ASIC布局器进行近似以实现效率。 不准确的模型被用来近似互连和放置者可能没有预留足够的资源路由。电路可能是不可布线的，并且可能需要设计迭代来收敛到具有良好质量的可行解。 本提案第一部分的目标是通过以下方式改进ASIC和结构化ASIC布局：（1）开发能够处理拥塞和阻塞的快速和可扩展的全局布线技术;以及（2）将全局布线集成到我们先前开发的布局技术中，这将导致更高质量的可布线布局。FPGA具有预定义的可布线布线结构。FPGA布局的重点是实现更好的时序。我们的第二部分建议将改善FPGA布局：（1）调查智能移动生成过程中的布局，这将产生更高的质量与更少的运行时间的布局;（2）改善包装基于集群的设备，也将改善result.This研究将产生新的和新颖的结果，将改善目前的国家的最先进的布局不同的设计风格。

Many issues confront modern IC designers: (1) circuits are large and require scalable algorithms; (2) different design styles are available, including ASICs, structured ASICs, and FPGAs; (3) designs have multiple objectives including wire length, routability and timing. Placement remains a pivotal step in physical design; it consumes significant run-time and largely determines the overall interconnect. Placement has enjoyed a renaissance in research activity in recent years.  The intent of this proposal to improve upon the state-of-the-art in placement for ASIC, structured ASIC, and FPGA design styles.ASIC and structured ASIC placers make approximations to achieve efficiency.  Inaccurate models are used to approximate interconnect and placers may not reserve enough resources for routing. A circuit may be unroutable and design iterations may be required to converge to a feasible  solution of good quality.  The objective of the first part of this proposal is to improve ASIC and structured ASIC placement by: (1) developing fast and scalable techniques for global routing which are capable of handling congestion and blockages; and (2) integrating global routing into our previously-developed placement technology that will result in higher quality placements which are routable.FPGAs have predefined routing structures that are designed to be routable. The emphasis in FPGA placement is on achieving better timing. The second part of our proposal will improve FPGA placement by:(1) investigating smart move generation during placement which will yield higher quality placements with less run-time; and (2) improving packing for cluster-based devices that will also improve results.This research will yield new and novel results that will improve upon the current state-of-the-art in placement for different design styles.