Methods for improving the physical optimization of asics structured asics and fpgas

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Many issues confront modern IC designers: (1) circuits are large and require scalable algorithms; (2) different design styles are available, including ASICs, structured ASICs, and FPGAs; (3) designs have multiple objectives including wire length, routability and timing. Placement remains a pivotal step in physical design; it consumes significant run-time and largely determines the overall interconnect. Placement has enjoyed a renaissance in research activity in recent years.  The intent of this proposal to improve upon the state-of-the-art in placement for ASIC, structured ASIC, and FPGA design styles.ASIC and structured ASIC placers make approximations to achieve efficiency.  Inaccurate models are used to approximate interconnect and placers may not reserve enough resources for routing. A circuit may be unroutable and design iterations may be required to converge to a feasible  solution of good quality.  The objective of the first part of this proposal is to improve ASIC and structured ASIC placement by: (1) developing fast and scalable techniques for global routing which are capable of handling congestion and blockages; and (2) integrating global routing into our previously-developed placement technology that will result in higher quality placements which are routable.FPGAs have predefined routing structures that are designed to be routable. The emphasis in FPGA placement is on achieving better timing. The second part of our proposal will improve FPGA placement by:(1) investigating smart move generation during placement which will yield higher quality placements with less run-time; and (2) improving packing for cluster-based devices that will also improve results.This research will yield new and novel results that will improve upon the current state-of-the-art in placement for different design styles.