Methods for improving the physical optimization of asics structured asics and fpgas

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Many issues confront modern IC designers: (1) circuits are large and require scalable algorithms; (2) different design styles are available, including ASICs, structured ASICs, and FPGAs; (3) designs have multiple objectives including wire length, routability and timing. Placement remains a pivotal step in physical design; it consumes significant run-time and largely determines the overall interconnect. Placement has enjoyed a renaissance in research activity in recent years. The intent of this proposal to improve upon the state-of-the-art in placement for ASIC, structured ASIC, and FPGA design styles.