On-chip instrumentation for analog / mixed-signal silicon debug, diagnosis and manufacturing test

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With the growing complexity of integrated circuits reaching the tens-of-million-plus transistor scale, electronic component and system manufacturers are moving towards a commence in third-party electronic component wares (called cores).  Besides the obvious need for standards to assist in their integration, the need for individual validation and final test is paramount to the overall product success.  From a digital design perspective, the appropriate design and test methodologies are, for the most part, already in place.  Scan chain techniques will continue to be used to move digital test information about a complex IC, regardless of the core origin.  In contrast, no simple method exists in which to move analog test information around an IC without serious degradation of its signal-to-noise ratio and high-frequency spectral content.  At the moment, on-chip sampling-scope-type circuits and time-to-digital converter circuits are showing great promise for observing signals on-chip at very high signal frequencies, as well with acceptable precision and accuracy. As the test information is sampled and converted into digital form, test information can be easily moved around the IC without loss of information and easily integrated into existing digital test structures, buses and protocols. Another important reason for the practical success of the on-chip sampling scope and time-to-digital converter is the fact that they require very little silicon area to implement. Furthermore, the impact on the performance of the circuit-under-test is minimal. Following similar considerations, this research project will consider developing other types of embedded circuits that can be used to observe signals directly on-chip.  As process variability affects all analog circuits, this project will further consider how such embedded instruments can be calibrated directly on-chip in real-time or off-chip through external digital control. The objective will be to construct circuits that require little silicon area and have little impact on the building block's power and performance. In all cases, experimental ICs will be constructed in state-of-the-art CMOS fabrication technologies made available through the Canadian Microsystems Corporation (CMC).