Design-for-test techniques for 60 GHz ISM radio applications

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With the availability of 7 GHz of unlicensed spectrum centered around 60 GHz, attention throughout the world is now focused on utilizing this resource for new consumer applications such as for high-data rate wireless transmission, automotive collision avoidance radar applications and automotive adaptive cruise control, to name just a few. Historically, the cost of 60 GHz electronics, implemented in compound semiconductor technology, has been prohibitively expensive. Today, it is believed that a fully integrated CMOS implementation will drive this cost to an acceptable consumer price point. However, before this happens, two important aspects of a fully integrated CMOS approach must be realized: low-cost packaging and low-cost production testing. It has been noted year after year in the international technology roadmap for semiconductors (ITRS) that packaging and test costs amount for at least two-thirds of the product cost of any mixed-signal or RF circuit. While important developments are taking place in the packaging arena, like bonding bare die directly on low-temperature co-fired ceramic substrates using flip-chip techniques, eliminating the package altogether, we are also seeing developments in the opposite direction. New 3D silicon technologies are enabling the realization of complex silicon systems using stacked dies using through-silicon-vias (TSVs). Such packaging techniques rely heavily on the availability of known-good-die to maintain high product yields. Regardless of the packaging assemble used, the importance of cost effective test techniques are central to any advancement in 60 GHz radios for the ISM frequency band. It is therefore the objective of this research program to identify possible production-oriented test techniques for 60 GHz radio. This research program will consider five major directions related exclusively with test: (1) on-chip instruments active during wafer and final test, (2) high-speed test of digital I/Os, (3) Wireless, non-contact testing, (4) tester on a die in 3D CMOS, and (5) adaptive test techniques for RF Circuits. All five directions will consider overall test time, yield loss and component costs.