Frontiers-based synthesis of digital logic

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Hardware description languages (HDL) have remained at a low semantic level, and have limited abstraction capabilities. These characteristics make the development of VLSI ASICs and FPGAs inherently more difficult and expensive. Research in programming languages and their semantics has established a path toward specification/implementation languages which have much cleaner semantics and strong powers of abstraction. It has been known that such languages could improve the processes of hardware description, synthesis, and verification. But the lack of a method of bridging the large semantic gap between the more powerful languages and Boolean gates has prevented practical progress in this direction. However, work by the applicant and a former PhD student has established an efficient means of synthesizing minimal gate implementations from these abstract languages. This method is based on the computation of frontiers in extended Boolean domains. The proposed work will: a) improve the theoretical basis of the earlier work, b) make the specification language richer and support the new features in the synthesizer, c) embed this specification langauge in Verilog, such that a full Verilog tool chain can be used in experiments, and d) in the longer term, extend this language into the asynchronous design domain which the VLSI community must sooner or later embrace.