High-performance, fault-tolerant, and energy-efficient control technology

高性能、容错、节能的控制技术

• 批准号: 283244-2009
• 负责人: Beguenane, Rachid
• 金额: $ 1.46万
• 依托单位: Royal Military College of Canada
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2011
• 资助国家: 加拿大
• 起止时间: 2011-01-01 至 2012-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=480330
• 关键词: performance; fault; tolerant; energy; efficient

Digital control is the heart of motion industry, and the associated algorithms can go from simple to more complex, with dynamics ranging from few microseconds to several tens of seconds. The need to perform complex computations with high real-time constraints has always been a major technological challenge for the development of advanced controllers. Thanks to major technological breakthroughs in recent years and sustained rapid progress in the areas of a massive scale integration and computer aided design tools, the realization of application specific chips becomes increasingly rapid and affordable, enabling electronic systems to cross new performance records. The reconfigurable FPGA permits now to design and validate quickly, in laboratory, any SoC. For low production volumes (few 1000s), the FPGA is economically advantageous as a final platform. For higher volume production, the description in the form of "netlist" of FPGA-based prototype of the controller can then be sent to an ICs fabric to be etched in silicon as an ASIC. However, as these new technologies are beginning to be used in digital control to overcome the limitations of microcontrollers and DSP processors used so far, new challenges are emerging due to several factors, including the difficulty for control specialists to work easily with these technologies, lack of design tools adapted for their needs, the increasing complexity of control algorithms to meet exigent dynamic, and the difficulty of implementing them in the form of ICs. The need for a research contribution to assist the development of generalized system on a chip for digital control is therefore felt. To meet this need, the main objective of the present proposal is to design and develop an effective technology that includes an easy design strategy and reusable hardware cores that are well adapted to both the user and performance criteria of the application. An FPGA platform will be used to support the proposed technology targeting real-time constraints no more than ten microseconds while keeping a low to moderate logic space for a cost-effective solution. The functionality and performance of this contribution will be demonstrated through some case studies of complex control AC drives.

数字控制是运动产业的核心，相关的算法可以从简单到复杂，动态范围从几微秒到几十秒不等。对于高级控制器的开发来说，执行具有高实时约束的复杂计算的需求一直是主要的技术挑战。由于近年来的重大技术突破和大规模集成和计算机辅助设计工具领域的持续快速进步，专用芯片的实现变得越来越快和负担得起，使电子系统能够打破新的性能纪录。可重构的现场可编程门阵列现在允许在实验室快速设计和验证任何SoC。对于较低的生产量(只有1000个)，作为最终平台，现场可编程门阵列具有经济优势。为了更大规模的生产，控制器原型的“网表”形式的描述可以发送到IC结构中，作为ASIC在硅中刻蚀。然而，随着这些新技术开始用于数字控制，以克服迄今使用的微控制器和DSP处理器的局限性，一些因素导致新的挑战出现，包括控制专家很难使用这些技术，缺乏适合他们需求的设计工具，控制算法越来越复杂，以满足紧急动态，以及以IC的形式实现它们的难度。因此，人们感到有必要做出研究贡献，以帮助开发用于数字控制的通用片上系统。为满足这一需要，本提案的主要目标是设计和开发一种有效的技术，其中包括一种简单的设计战略和能够很好地适应用户和应用程序性能标准的可重复使用的硬件核心。一个现场可编程门阵列平台将被用来支持所提出的技术，目标是实时约束不超过十微秒，同时保持低到中等的逻辑空间，以实现经济高效的解决方案。这一贡献的功能和性能将通过一些复杂控制交流驱动器的案例研究来展示。