Ultra-Compact Low-Power Photonic Network-on-Chip

随着微电子芯片计算能力的提高，由于速度和晶体管密度的不断提高，它们产生的信息流变得越来越难以处理。因此，芯片之间的电互连，甚至芯片内逻辑单元之间的电互连都成为瓶颈。随着总带宽超过1 Tb/s，光网络已经展示了光传输信息的潜力，现在它可以用来解决芯片规模上出现的挑战。硅光子学已经证明，光学器件可以使用CMOS兼容工艺制造，但要在同一芯片上有效地结合光学电路和电子电路，仍有许多挑战必须解决。例如，对硅和绝缘体上硅晶圆的埋地氧化层的要求很大程度上取决于它们是用于光学还是电子应用。

As the computing capacity of microelectronic chips increases, thanks to continuous improvements in speed and transistor density, the flows of information they generate are becoming harder to handle. As a result, the electrical interconnections between chips and even between logical units within a chip are becoming bottlenecks. With aggregate bandwidths exceeding one Tb/s, optical networks have demonstrated the potential of light to transmit information, and now it can be used to resolve the challenges arising at the chip scale. Silicon photonics has demonstrated that optical devices can be manufactured using CMOS compatible processes but there are still numerous challenges that must be addressed to efficiently combine optical and electronic circuits on the same chip. For instance, the requirements on the silicon and buried oxide layers of silicon-on-insulator wafers differ greatly depending on whether they are used for optical or electronic applications.