Energy-Efficient Computation and its Application to Baseband Signal Processing Systems

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The proposed research program investigates energy-efficient integrated circuit realizations of baseband communications and signal processing algorithms, such as those used in recent wireless and wireline systems. To achieve near-capacity performance, modern communication standards use forward error correction such as Turbo or low-density parity-check (LDPC) coding, with high-speed (e.g. IEEE 802.3an for 10 Gb/s Ethernet) or low power consumption requirements (e.g. IEEE 802.11n, IEEE 802.16m, and 4th-generation (4G) wireless (e.g. Long-Term Evolution, LTE)). The proposed research has the potential to make decoding feasible for high-speed or energy-constrained emerging areas such as 100+ Gb/s Ethernet and body-area networks. Due to their numerically intensive nature, decoders can consume significant power, especially for high-speed implementations. In recent years, very impressive LDPC and Turbo decoders have been demonstrated in complementary metal oxide semiconductor (CMOS) technologies, with some decoders consuming as little as a few tens of picojoules per transmitted bit. Despite these results, there remain many open scientific issues. (1) Most of the techniques require parallel processing and are only applicable to short-to-moderate block length codes (i.e. up to a few 1000's of bits). Longer codes have better error-correcting capabilities but parallelism cannot be fully exploited due to area limitations. (2) To adapt to time-varying channel characteristics, standards often define several code rates. The most efficient decoder implementations often realize only one of the code rates (e.g. R = 1/2). Satisfying multiple rates requires configurability, which comes at the cost of energy efficiency. (3) Since the design space for LDPC and Turbo decoders is immense, decoders can yet be made to be far more energy efficient, for instance by aggressively scaling supply voltages. The proposed research program will investigate the issues above. The techniques will first be verified using high-level simulations, and will ultimately be demonstrated through extensive tests and power measurements from proof-of-concept integrated circuits designed by the HQP as part of their research and training program.