Energy-Efficient Computation and its Application to Baseband Signal Processing Systems

拟议的研究计划研究基带的高能效集成电路实现 通信和信号处理算法，例如在最近的无线和有线系统中使用的算法。为了实现接近容量的性能，现代通信标准使用前向纠错，例如Turbo或低密度奇偶校验(LDPC)编码，具有高速(例如，用于10 Gb/S以太网的IEEE802.3an)或低功耗要求(例如，IEEE802.11n、IEEE802.16m和第四代(4G)无线(例如，长期演进，LTE))。这项拟议的研究有可能使解码适用于高速或能源受限的新兴领域，如100+Gb/S以太网和体域网络。由于其数值密集的特性，解码器可能会消耗大量的功率，特别是对于高速实现而言。近年来，在互补金属氧化物半导体(CMOS)技术中展示了非常令人印象深刻的LDPC和Turbo译码，一些译码每传输比特的功耗低至几十皮焦耳。尽管有这些结果，但仍有许多科学问题悬而未决。(1)大多数技术需要并行处理，并且仅适用于短到中的块长度代码(即，最多几个1000‘S比特)。较长的代码具有更好的纠错能力，但由于区域限制，并行性不能得到充分利用。(2)为了适应时变的信道特性，标准通常定义几种码率。最有效的解码器实现通常仅实现码率之一(例如，R=1/2)。满足多个速率需要可配置性，这是以能源效率为代价的。(3)由于LDPC和Turbo解码器的设计空间很大，解码器仍可通过积极调整电源电压等方式来实现更高的能效。拟议的研究计划将对上述问题进行研究。这些技术将首先使用高级模拟进行验证，最终将通过广泛的测试和来自HQP设计的概念验证集成电路的功率测量来演示，这是他们研究和培训计划的一部分。

The proposed research program investigates energy-efficient integrated circuit realizations of baseband communications and signal processing algorithms, such as those used in recent wireless and wireline systems. To achieve near-capacity performance, modern communication standards use forward error correction such as Turbo or low-density parity-check (LDPC) coding, with high-speed (e.g. IEEE 802.3an for 10 Gb/s Ethernet) or low power consumption requirements (e.g. IEEE 802.11n, IEEE 802.16m, and 4th-generation (4G) wireless (e.g. Long-Term Evolution, LTE)). The proposed research has the potential to make decoding feasible for high-speed or energy-constrained emerging areas such as 100+ Gb/s Ethernet and body-area networks. Due to their numerically intensive nature, decoders can consume significant power, especially for high-speed implementations. In recent years, very impressive LDPC and Turbo decoders have been demonstrated in complementary metal oxide semiconductor (CMOS) technologies, with some decoders consuming as little as a few tens of picojoules per transmitted bit. Despite these results, there remain many open scientific issues. (1) Most of the techniques require parallel processing and are only applicable to short-to-moderate block length codes (i.e. up to a few 1000's of bits). Longer codes have better error-correcting capabilities but parallelism cannot be fully exploited due to area limitations. (2) To adapt to time-varying channel characteristics, standards often define several code rates. The most efficient decoder implementations often realize only one of the code rates (e.g. R = 1/2). Satisfying multiple rates requires configurability, which comes at the cost of energy efficiency. (3) Since the design space for LDPC and Turbo decoders is immense, decoders can yet be made to be far more energy efficient, for instance by aggressively scaling supply voltages. The proposed research program will investigate the issues above. The techniques will first be verified using high-level simulations, and will ultimately be demonstrated through extensive tests and power measurements from proof-of-concept integrated circuits designed by the HQP as part of their research and training program.