Computer Aided Design Tools for FPGA Exploration

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Over the past 50 years, advances in Integrated Circuit fabrication technology have enabled society to progress faster than ever before. As integration continues its exponential progress, however, the complexity of the underlying fabrication technology, the expertise required to exploit it, and the financial risks associated with each deployment have also grown at an exponential rate. Field-Programmable Gate Arrays (FPGAs) have become the implementation medium of choice for many of these crucial applications of digital circuits. FPGAs can be configured to implement any circuit, allowing designers to immediately test designs without the cost, risk and delay of producing a fully-customized chip. They provide companies with large-scale integration without requiring access to a state-of-the-art chip fabrication plant. This is crucial; the cost of building an integrated circuit is rising dramatically, and is far out of reach for most small and medium sized Canadian electronics companies. Without FPGAs, these companies will be unable to economically produce equipment that can compete with their counterparts internationally. In order for FPGAs to find greater acceptance in the market place, new heterogeneous FPGA architectures need to be explored for greater suitability to various application domains. To effectively utilize heterogeneous architectures, the Computer-Aided Design (CAD) flow must be aware of the target FPGA architecture and perform high-level compilation, synthesis, placement and routing accordingly. I have completed preliminary research in this area through the front end (verilog compilation) of the Verilog-to-Routing (VTR) academic CAD flow. Based on this, in the current research I will investigate the CAD flow for new heterogeneous energy-efficient FPGA architectures and circuits, and methods for mapping applications to FPGAs with performance and energy as primary concerns.