Computer Aided Design Tools for FPGA Exploration

在过去的50年里，集成电路制造技术的进步使社会比以往任何时候都进步得更快。然而，随着集成继续呈指数级增长，底层制造技术的复杂性、利用它所需的专业知识以及与每次部署相关的财务风险也以指数级速度增长。现场可编程门阵列（FPGA）已成为许多关键数字电路应用的首选实现介质。FPGA可以配置为实现任何电路，允许设计人员立即测试设计，而无需生产完全定制的芯片的成本，风险和延迟。它们为公司提供大规模集成，而无需访问最先进的芯片制造工厂。这一点至关重要;制造集成电路的成本正在急剧上升，对于大多数中小型加拿大电子公司来说，这是遥不可及的。如果没有FPGA，这些公司将无法经济地生产出能够与国际同行竞争的设备。为了让FPGA在市场上获得更大的认可，需要探索新的异构FPGA架构，以更好地适应各种应用领域。为了有效地利用异构体系结构，计算机辅助设计（CAD）流程必须了解目标FPGA体系结构，并相应地执行高级编译、综合、布局和布线。我已经通过Verilog到Routing（VTR）学术CAD流程的前端（verilog编译）完成了这方面的初步研究。基于此，在目前的研究中，我将研究新的异构节能FPGA架构和电路的CAD流程，以及将应用程序映射到FPGA的方法，性能和能源作为主要关注点。

Over the past 50 years, advances in Integrated Circuit fabrication technology have enabled society to progress faster than ever before. As integration continues its exponential progress, however, the complexity of the underlying fabrication technology, the expertise required to exploit it, and the financial risks associated with each deployment have also grown at an exponential rate. Field-Programmable Gate Arrays (FPGAs) have become the implementation medium of choice for many of these crucial applications of digital circuits. FPGAs can be configured to implement any circuit, allowing designers to immediately test designs without the cost, risk and delay of producing a fully-customized chip. They provide companies with large-scale integration without requiring access to a state-of-the-art chip fabrication plant. This is crucial; the cost of building an integrated circuit is rising dramatically, and is far out of reach for most small and medium sized Canadian electronics companies. Without FPGAs, these companies will be unable to economically produce equipment that can compete with their counterparts internationally.In order for FPGAs to find greater acceptance in the market place, new heterogeneous FPGA architectures need to be explored for greater suitability to various application domains. To effectively utilize heterogeneous architectures, the Computer-Aided Design (CAD) flow must be aware of the target FPGA architecture and perform high-level compilation, synthesis, placement and routing accordingly. I have completed preliminary research in this area through the front end (verilog compilation) of the Verilog-to-Routing (VTR) academic CAD flow. Based on this, in the current research I will investigate the CAD flow for new heterogeneous energy-efficient FPGA architectures and circuits, and methods for mapping applications to FPGAs with performance and energy as primary concerns.