Computer Aided Design Tools for FPGA Exploration

用于 FPGA 探索的计算机辅助设计工具

• 批准号: 262177-2012
• 负责人: Kent, Kenneth
• 金额: $ 1.31万
• 依托单位: University of New Brunswick
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637707
• 关键词: Computer; Aided; Design; Tools; FPGA

Over the past 50 years, advances in Integrated Circuit fabrication technology have enabled society to progress faster than ever before. As integration continues its exponential progress, however, the complexity of the underlying fabrication technology, the expertise required to exploit it, and the financial risks associated with each deployment have also grown at an exponential rate. Field-Programmable Gate Arrays (FPGAs) have become the implementation medium of choice for many of these crucial applications of digital circuits. FPGAs can be configured to implement any circuit, allowing designers to immediately test designs without the cost, risk and delay of producing a fully-customized chip. They provide companies with large-scale integration without requiring access to a state-of-the-art chip fabrication plant. This is crucial; the cost of building an integrated circuit is rising dramatically, and is far out of reach for most small and medium sized Canadian electronics companies. Without FPGAs, these companies will be unable to economically produce equipment that can compete with their counterparts internationally.In order for FPGAs to find greater acceptance in the market place, new heterogeneous FPGA architectures need to be explored for greater suitability to various application domains. To effectively utilize heterogeneous architectures, the Computer-Aided Design (CAD) flow must be aware of the target FPGA architecture and perform high-level compilation, synthesis, placement and routing accordingly. I have completed preliminary research in this area through the front end (verilog compilation) of the Verilog-to-Routing (VTR) academic CAD flow. Based on this, in the current research I will investigate the CAD flow for new heterogeneous energy-efficient FPGA architectures and circuits, and methods for mapping applications to FPGAs with performance and energy as primary concerns.

在过去的50年中，综合电路制造技术的进步使社会能够比以往任何时候都更快。然而，随着整合持续其指数进步，基本制造技术的复杂性，利用它所需的专业知识以及与每次部署相关的财务风险也以指数级的速度增长。现场可编程的门阵列（FPGA）已成为许多这些关键的数字电路应用的实现媒介。可以将FPGA配置为实现任何电路，使设计人员可以立即测试设计，而无需成本，风险和延迟产生完全定制的芯片。他们为公司提供大规模集成，而无需使用最先进的芯片制造厂。这是至关重要的；建造综合电路的成本正在急剧上升，对于大多数中小型加拿大电子公司而言，遥不可及。如果没有FPGA，这些公司将无法在经济上生产能够与国际上方竞争的设备。为了让FPGA在市场上找到更大的接受，需要探索新的异质FPGA体系结构，以使其更大的适用性对各种应用领域。为了有效利用异质体系结构，计算机辅助设计（CAD）流必须了解目标FPGA架构并相应地执行高级汇编，合成，放置和路由。我已经完成了该领域的初步研究，通过Verilog-Routing（VTR）学术CAD流的前端（Verilog汇编）。基于此，在当前的研究中，我将研究新的异质能节能FPGA体系结构和电路的CAD流，以及将应用程序映射到具有性能和能量作为主要问题的FPGA的方法。