High-Level Design for FPGAs and Embedded Systems

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Field-programmable gate arrays (FPGAs) are integrated circuits that can be programmed by an end user to implement any digital hardware circuit. A relatively new use of FPGAs is in compute acceleration, where parts of a computational algorithm are executed in software on a CPU and other parts are implemented as hardware accelerators in an FPGA. Accelerating an algorithm in this way offers an order of magnitude improvement over software running on a processor in terms of energy efficiency and/or performance for some applications. The development of such hybrid systems remains a challenge in the industry, requiring manual partitioning of algorithms into software and hardware, and manual coding of hardware using languages like Verilog or VHDL. The research in this proposed Discovery Grant is intended to improve the state-of-the-art in this area by automatically generating hybrid hardware/software implementations.******Over the past three years, the applicant's research group has created an open-source research framework called LegUp. It is able to automatically partition a compute-intensive algorithm written in the C programming language into software parts running on a processor, and hardware parts implemented in an FPGA. The system is able to automatically identify and produce the hardware parts from the original C code, with no manual hardware design. LegUp produces hardware circuits from C code by using a combination of profiling and high-level-synthesis algorithms.***LegUp is available online and has been downloaded by over 1,000 research groups worldwide. In the proposed research, the LegUp tool will be enhanced extensively. One topic will involve the generation of faster hardware in the form of streaming circuits, as opposed to the currently-generated data-path and control circuits. Support will be added for ARM processors, which are very popular in the industry, so that LegUp can produce automatically hybrid systems involving both ARM processors and hardware accelerators; currently LegUp supports only MIPs processors.******As a longer-term goal the proposed research will attempt to automatically generate hardware accelerators from processor machine code, rather than the source code of a program. In this approach, parts of the machine code executing on a processor will be identified automatically using profiling, at run-time, for hardware acceleration. This machine code will be disassembled by LegUp into assembly language code and then compiled into Verilog code to make hardware accelerators, using much of the capability that already exists in the LegUp infrastructure. If successful, this approach would engender the automatic acceleration of any program running on a computer that has an FPGA and the LegUp tools installed. If an FPGA were included in mainstream computers, and the LegUp tools were installed, then even users of home and/or office computers would have access to hardware acceleration.**