Variation-Adaptive Design in FPGAs

这一建议涉及的设计技术，以补偿参数变化的深亚微米可配置数字电路。在过去的四十年里，微电子工业的发展一直是基于减小晶体管的尺寸，使集成电路更小、更快、更便宜。由于在单个芯片内控制参数的扩散变得越来越困难，晶体管缩放所带来的好处正在减少。本提案的研究将探讨深亚微米可编程逻辑器件中新的变化感知设计技术。这与最近开发的微电子大挑战“路线图，特别是GC3- Moore for Less”非常一致。本研究的前提是单一设计可以在给定的可编程逻辑器件中以多种方式实现。在存在变化的情况下，不同的实现将表现出不同的性能，尽管它们在功能上是相同的。目的是发现和开发利用现有可编程逻辑器件的这一特性的策略。此外，将提出对这些装置进行结构修改，以增加可获得的效益。这些目标将通过从实证研究中对参数变异性的本质进行彻底分析，然后严格使用概率建模和优化理论来实现。

This proposal is concerned with design techniques to compensate for parametric variations in deep-submicron configurable digital circuits. The growth of the microelectronics industry over the last four decades has been based on reducing the size of transistors to make integrated circuits smaller, faster and less expensive. The benefits obtained by transistor scaling are now diminishing as it becomes increasingly difficult to control the spread of parameters within a single chip.The research in this proposal will investigate new variation-aware design techniques in deep-submicron programmable logic devices. This is well-aligned with the recently developed Microelectronics Grand Challenges'' roadmap, particularly GC3---Moore for Less''. The premise for the research is that a single design can be implemented in more than one way in a given programmable logic device. In the presence of variations, distinct implementations will exhibit different performances, although they are functionally identical.The intention is to discover and develop strategies which exploit this feature in existing programmable logic devices. Furthermore, architectural modifications to such devices will be proposed to increase the obtainable benefit. These goals will be achieved from a thorough analysis of the nature of parametric variability from empirical studies, followed by the rigorous use of probabilistic modelling and optimisation theory.