Signal Processors and their Architectures for Relay-Assisted Communication Systems

在中继网络中，中继站(RS)被放置在基站(BS)和目的站(DS)之间，而RS在BS和DS之间协作接收和重发数据。中继的提出是为了提高网络吞吐量和扩大覆盖范围，或者促进非许可用户和许可用户之间的合作，以缓解频谱未充分利用或剥夺。长期演进推进(LTE-A)无线标准规定了固定中继站为基站覆盖区域之外的移动用户提供规定的数据吞吐量。在文献中的几种中继传输协议中，最受关注的是分布式空时分组码(DSTBC)和多输入多输出(MIMO)的放大转发(AF)协议，它是提供协作分集的有效手段。然而，协作会产生干扰和同步问题，从而降低性能。目标是开发新的和深入的知识，以构建低复杂性、节能、高速、健壮的处理器和体系结构，以处理具有AF和DSTBC的中继网络中的多媒体服务。提出的研究集中于推导新的递归(最优和次优)信号处理算法(基于雅可比旋转)和结构(基于脉动阵列)，用于(I)信道估计，(Ii)干扰消除，(Iii)收发信机优化，(Iv)算法在现场可编程门阵列(FPGA)平台上的映射，以及(V)算法的软件定义无线电(SDR)实现。信道状态信息(CSI)估计、干扰消除和收发信机优化是系统整体性能的关键，而它们构成了系统中最密集的任务。然而，对于无线应用，低复杂度、低功耗、高速和稳定(健壮)的体系结构是非常需要的。为了实现低复杂性和高速度的实现，体系结构必须是高度流水线的，并且在如何处理数据方面具有并行性。使用雅可比旋转将产生具有内在并行性和计算稳定性的方法。脉动阵列是高度流水线的并行结构，可以利用基于雅可比旋转的方法的并行性来加速信号处理。对于这种体系结构的SDR实现，需要将算法映射到典型的FPGA处理器上。在该方案中，我们将推导出用于信道估计、干扰消除和收发信机操作的递归最优算法。信道估计将在DS处进行(不是为了给RS增加负担)，并分解为BS-RS和RS-DS链路分量。分解将通过非对称复值矩阵的基于雅可比旋转的奇异值分解(SVD)和Kronecker积来促进。将部分使用雅可比旋转和子空间方法来推导新的信道估计和接收器优化算法。现有和新的算法将在复杂性、速度和功率方面进行优化。这些算法将针对映射和在特定的FPGA平台上的高效实现进行优化。将分析脉动阵列的实施速度和计算强度。*影响：结果将有助于(A)了解1)将获得的整体利益，2)扩大覆盖范围和提高吞吐量的影响，3)频谱利用不足或缺乏的好处，(B)具有复杂性和功率限制的中继辅助系统的有效部署，2)为特定的FPGA平台确定正确的算法，3)向加拿大工业传递知识，4)培训HQP和5)向学术界/研究界注入新知识。

In relay networks, relay stations (RS) are placed between base station (BS) and destination station (DS), while the RS cooperatively receive and retransmit data between BS and DS. Relays are proposed to enhance network throughput and extend coverage or facilitate cooperation among unlicensed and licensed users in order to alleviate spectral under-utilization or deprivation. The Long Term Evolution Advance (LTE-A) wireless standard has provisions for fixed relays to deliver prescribed data throughput for mobile users outside the coverage area of a base-station. Of the several relay transmission protocols in the literature, the one that has received the most attention is the amplify-and-forward (AF) with distributed space time block codes (DSTBC) and multiple-input multiple-output (MIMO) for its efficient means of providing cooperative diversity. However, cooperation creates interference and synchronization problems, which degrade performance. The objective is to develop new and in-depth knowledge towards the construction of low-complexity, power efficient, high-speed, robust processors and architectures to handle multimedia services in relay networks with AF and DSTBC. The proposed research focuses on derivation of novel recursive (optimal and suboptimal) signal processing algorithms (based on Jacobi rotations) and architectures (based on systolic arrays) for (i) channel estimation, (ii) interference cancellation, (iii) transceiver optimization, (iv) mapping of algorithms on field programmable gate array (FPGA) platforms, and (v) software defined radio (SDR) implementation of the algorithms. Channel state information (CSI) estimation, interference cancellation and transceiver optimization are critical for the overall system performance while they form the most intensive tasks in the system. For wireless applications, however, low-complexity, low-power, high-speed and stable (robust) architectures are highly desired. To accomplish low-complexity and high speed implementation, architectures must be highly pipelined and possess parallelism, with respect to how data is processed. The use of Jacobi rotation will result in methods with inherent parallelism and computational stability. Systolic arrays are highly pipelined, parallel structures, which can exploit the parallelism of Jacobi rotation-based methods to speed up signal processing. For SDR implementation of such architectures, it is required to map algorithms on a typical FPGA processor. In this proposal, we shall derive recursive, optimal algorithms for channel estimation, interference cancellation and transceiver operation. Channel estimation will be done at the DS (not to burden the RS) and decomposed into BS-RS and RS-DS link components. Decomposition will be facilitated by Jacobi rotation-based singular value decomposition (SVD) for non-symmetric complex-valued matrices and the Kronecker product. Novel channel estimation and receiver optimization algorithms will be derived, in part, using Jacobi rotation and subspace methods. Existing and new algorithms will be optimized for complexity, speed and power. The algorithms will be optimized for mapping and efficient implementation on specific FPGA platforms. Systolic array implementations will be analyzed for speed and computational intensiveness.*Impact: Results will aid (a) understanding of 1) overall benefits to be gained, 2) effects on extending coverage and enhanced throughput, 3) benefits on spectral under-utilization or deprivation, (b) 1) efficient deployment of relay-assisted systems with complexity and power constraints, 2) identification of the right algorithms for specific FPGA platforms, 3) knowledge transfer to Canadian industry, 4) training of HQP and 5) injection of new knowledge to the academic/research community.