Signal Processors and their Architectures for Relay-Assisted Communication Systems

用于中继辅助通信系统的信号处理器及其架构

• 批准号: RGPIN-2014-04456
• 负责人: Sesay, Abu
• 金额: $ 1.82万
• 依托单位: University of Calgary
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637305
• 关键词: Signal; Processors; their; Architectures; Relay

In relay networks, relay stations (RS) are placed between base station (BS) and destination station (DS), while the RS cooperatively receive and retransmit data between BS and DS. Relays are proposed to enhance network throughput and extend coverage or facilitate cooperation among unlicensed and licensed users in order to alleviate spectral under-utilization or deprivation. The Long Term Evolution Advance (LTE-A) wireless standard has provisions for fixed relays to deliver prescribed data throughput for mobile users outside the coverage area of a base-station. Of the several relay transmission protocols in the literature, the one that has received the most attention is the amplify-and-forward (AF) with distributed space time block codes (DSTBC) and multiple-input multiple-output (MIMO) for its efficient means of providing cooperative diversity. However, cooperation creates interference and synchronization problems, which degrade performance. The objective is to develop new and in-depth knowledge towards the construction of low-complexity, power efficient, high-speed, robust processors and architectures to handle multimedia services in relay networks with AF and DSTBC. The proposed research focuses on derivation of novel recursive (optimal and suboptimal) signal processing algorithms (based on Jacobi rotations) and architectures (based on systolic arrays) for (i) channel estimation, (ii) interference cancellation, (iii) transceiver optimization, (iv) mapping of algorithms on field programmable gate array (FPGA) platforms, and (v) software defined radio (SDR) implementation of the algorithms. Channel state information (CSI) estimation, interference cancellation and transceiver optimization are critical for the overall system performance while they form the most intensive tasks in the system. For wireless applications, however, low-complexity, low-power, high-speed and stable (robust) architectures are highly desired. To accomplish low-complexity and high speed implementation, architectures must be highly pipelined and possess parallelism, with respect to how data is processed. The use of Jacobi rotation will result in methods with inherent parallelism and computational stability. Systolic arrays are highly pipelined, parallel structures, which can exploit the parallelism of Jacobi rotation-based methods to speed up signal processing. For SDR implementation of such architectures, it is required to map algorithms on a typical FPGA processor. In this proposal, we shall derive recursive, optimal algorithms for channel estimation, interference cancellation and transceiver operation. Channel estimation will be done at the DS (not to burden the RS) and decomposed into BS-RS and RS-DS link components. Decomposition will be facilitated by Jacobi rotation-based singular value decomposition (SVD) for non-symmetric complex-valued matrices and the Kronecker product. Novel channel estimation and receiver optimization algorithms will be derived, in part, using Jacobi rotation and subspace methods. Existing and new algorithms will be optimized for complexity, speed and power. The algorithms will be optimized for mapping and efficient implementation on specific FPGA platforms. Systolic array implementations will be analyzed for speed and computational intensiveness.Impact: Results will aid (a) understanding of 1) overall benefits to be gained, 2) effects on extending coverage and enhanced throughput, 3) benefits on spectral under-utilization or deprivation, (b) 1) efficient deployment of relay-assisted systems with complexity and power constraints, 2) identification of the right algorithms for specific FPGA platforms, 3) knowledge transfer to Canadian industry, 4) training of HQP and 5) injection of new knowledge to the academic/research community.

在中继网络中，中继站(RS)放置在基站(BS)和目的站(DS)之间，而RS在BS和DS之间协作接收和重传数据。建议使用中继来增强网络吞吐量并扩大覆盖范围或促进未授权和授权用户之间的合作，以减轻频谱利用不足或剥夺的情况。长期演进高级 (LTE-A) 无线标准规定固定中继可为基站覆盖区域外的移动用户提供规定的数据吞吐量。在文献中的几种中继传输协议中，最受关注的一种是具有分布式空时分组码（DSTBC）和多输入多输出（MIMO）的放大转发（AF）协议，因为它能够有效地提供协作分集。然而，协作会产生干扰和同步问题，从而降低性能。目标是开发新的、深入的知识，以构建低复杂性、高能效、高速、强大的处理器和架构，以处理具有 AF 和 DSTBC 的中继网络中的多媒体服务。拟议的研究重点是推导新颖的递归（最优和次优）信号处理算法（基于雅可比旋转）和架构（基于脉动阵列），用于（i）信道估计，（ii）干扰消除，（iii）收发器优化，（iv）现场可编程门阵列（FPGA）平台上的算法映射，以及（v）软件 定义无线电 (SDR) 算法的实现。信道状态信息 (CSI) 估计、干扰消除和收发器优化对于整体系统性能至关重要，同时它们也是系统中最密集的任务。然而，对于无线应用来说，非常需要低复杂性、低功耗、高速和稳定（鲁棒）的架构。为了实现低复杂性和高速实现，架构必须高度流水线化并在数据处理方式方面具有并行性。雅可比旋转的使用将产生具有固有并行性和计算稳定性的方法。脉动阵列是高度流水线化的并行结构，可以利用基于雅可比旋转的方法的并行性来加速信号处理。对于此类架构的 SDR 实现，需要将算法映射到典型的 FPGA 处理器上。在本提案中，我们将推导出用于信道估计、干扰消除和收发器操作的递归最优算法。信道估计将在 DS 处完成（不会给 RS 带来负担）并分解为 BS-RS 和 RS-DS 链路组件。非对称复值矩阵和克罗内克积的基于雅可比旋转的奇异值分解 (SVD) 将促进分解。新的信道估计和接收机优化算法将部分地使用雅可比旋转和子空间方法来推导。现有的和新的算法将针对复杂性、速度和功率进行优化。这些算法将针对特定 FPGA 平台上的映射和高效实施进行优化。将分析脉动阵列实现的速度和计算密集度。影响：结果将有助于 (a) 了解 1) 获得的总体效益，2) 对扩大覆盖范围和增强吞吐量的影响，3) 对频谱利用不足或剥夺的效益，(b) 1) 有效部署具有复杂性和功耗限制的中继辅助系统，2) 识别特定 FPGA 平台的正确算法， 3) 向加拿大工业界转移知识，4) 总部人员培训，5) 向学术/研究界注入新知识。