Signal Processors and their Architectures for Relay-Assisted Communication Systems

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In relay networks, relay stations (RS) are placed between base station (BS) and destination station (DS), while the RS cooperatively receive and retransmit data between BS and DS. Relays are proposed to enhance network throughput and extend coverage or facilitate cooperation among unlicensed and licensed users in order to alleviate spectral under-utilization or deprivation. The Long Term Evolution Advance (LTE-A) wireless standard has provisions for fixed relays to deliver prescribed data throughput for mobile users outside the coverage area of a base-station. Of the several relay transmission protocols in the literature, the one that has received the most attention is the amplify-and-forward (AF) with distributed space time block codes (DSTBC) and multiple-input multiple-output (MIMO) for its efficient means of providing cooperative diversity. However, cooperation creates interference and synchronization problems, which degrade performance. The objective is to develop new and in-depth knowledge towards the construction of low-complexity, power efficient, high-speed, robust processors and architectures to handle multimedia services in relay networks with AF and DSTBC. The proposed research focuses on derivation of novel recursive (optimal and suboptimal) signal processing algorithms (based on Jacobi rotations) and architectures (based on systolic arrays) for (i) channel estimation, (ii) interference cancellation, (iii) transceiver optimization, (iv) mapping of algorithms on field programmable gate array (FPGA) platforms, and (v) software defined radio (SDR) implementation of the algorithms. Channel state information (CSI) estimation, interference cancellation and transceiver optimization are critical for the overall system performance while they form the most intensive tasks in the system. For wireless applications, however, low-complexity, low-power, high-speed and stable (robust) architectures are highly desired. To accomplish low-complexity and high speed implementation, architectures must be highly pipelined and possess parallelism, with respect to how data is processed. The use of Jacobi rotation will result in methods with inherent parallelism and computational stability. Systolic arrays are highly pipelined, parallel structures, which can exploit the parallelism of Jacobi rotation-based methods to speed up signal processing. For SDR implementation of such architectures, it is required to map algorithms on a typical FPGA processor. In this proposal, we shall derive recursive, optimal algorithms for channel estimation, interference cancellation and transceiver operation. Channel estimation will be done at the DS (not to burden the RS) and decomposed into BS-RS and RS-DS link components. Decomposition will be facilitated by Jacobi rotation-based singular value decomposition (SVD) for non-symmetric complex-valued matrices and the Kronecker product. Novel channel estimation and receiver optimization algorithms will be derived, in part, using Jacobi rotation and subspace methods. Existing and new algorithms will be optimized for complexity, speed and power. The algorithms will be optimized for mapping and efficient implementation on specific FPGA platforms. Systolic array implementations will be analyzed for speed and computational intensiveness.Impact: Results will aid (a) understanding of 1) overall benefits to be gained, 2) effects on extending coverage and enhanced throughput, 3) benefits on spectral under-utilization or deprivation, (b) 1) efficient deployment of relay-assisted systems with complexity and power constraints, 2) identification of the right algorithms for specific FPGA platforms, 3) knowledge transfer to Canadian industry, 4) training of HQP and 5) injection of new knowledge to the academic/research community.