Signal Processors and their Architectures for Relay-Assisted Communication Systems

用于中继辅助通信系统的信号处理器及其架构

• 批准号: RGPIN-2014-04456
• 负责人: Sesay, Abu
• 金额: $ 1.82万
• 依托单位: University of Calgary
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2016
• 资助国家: 加拿大
• 起止时间: 2016-01-01 至 2017-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=611049
• 关键词: Signal; Processors; their; Architectures; Relay

In relay networks, relay stations (RS) are placed between base station (BS) and destination station (DS), while the RS cooperatively receive and retransmit data between BS and DS. Relays are proposed to enhance network throughput and extend coverage or facilitate cooperation among unlicensed and licensed users in order to alleviate spectral under-utilization or deprivation. The Long Term Evolution Advance (LTE-A) wireless standard has provisions for fixed relays to deliver prescribed data throughput for mobile users outside the coverage area of a base-station. Of the several relay transmission protocols in the literature, the one that has received the most attention is the amplify-and-forward (AF) with distributed space time block codes (DSTBC) and multiple-input multiple-output (MIMO) for its efficient means of providing cooperative diversity. However, cooperation creates interference and synchronization problems, which degrade performance. The objective is to develop new and in-depth knowledge towards the construction of low-complexity, power efficient, high-speed, robust processors and architectures to handle multimedia services in relay networks with AF and DSTBC. The proposed research focuses on derivation of novel recursive (optimal and suboptimal) signal processing algorithms (based on Jacobi rotations) and architectures (based on systolic arrays) for (i) channel estimation, (ii) interference cancellation, (iii) transceiver optimization, (iv) mapping of algorithms on field programmable gate array (FPGA) platforms, and (v) software defined radio (SDR) implementation of the algorithms. Channel state information (CSI) estimation, interference cancellation and transceiver optimization are critical for the overall system performance while they form the most intensive tasks in the system. For wireless applications, however, low-complexity, low-power, high-speed and stable (robust) architectures are highly desired. To accomplish low-complexity and high speed implementation, architectures must be highly pipelined and possess parallelism, with respect to how data is processed. The use of Jacobi rotation will result in methods with inherent parallelism and computational stability. Systolic arrays are highly pipelined, parallel structures, which can exploit the parallelism of Jacobi rotation-based methods to speed up signal processing. For SDR implementation of such architectures, it is required to map algorithms on a typical FPGA processor. In this proposal, we shall derive recursive, optimal algorithms for channel estimation, interference cancellation and transceiver operation. Channel estimation will be done at the DS (not to burden the RS) and decomposed into BS-RS and RS-DS link components. Decomposition will be facilitated by Jacobi rotation-based singular value decomposition (SVD) for non-symmetric complex-valued matrices and the Kronecker product. Novel channel estimation and receiver optimization algorithms will be derived, in part, using Jacobi rotation and subspace methods. Existing and new algorithms will be optimized for complexity, speed and power. The algorithms will be optimized for mapping and efficient implementation on specific FPGA platforms. Systolic array implementations will be analyzed for speed and computational intensiveness. Impact: Results will aid (a) understanding of 1) overall benefits to be gained, 2) effects on extending coverage and enhanced throughput, 3) benefits on spectral under-utilization or deprivation, (b) 1) efficient deployment of relay-assisted systems with complexity and power constraints, 2) identification of the right algorithms for specific FPGA platforms, 3) knowledge transfer to Canadian industry, 4) training of HQP and 5) injection of new knowledge to the academic/research community.

在中继网络中，中继站（RS）位于基站（BS）和目的站（DS）之间，RS在基站（BS）和目的站（DS）之间协同接收和转发数据。建议使用中继来提高网络吞吐量和扩大覆盖范围，或促进未授权和授权用户之间的合作，以缓解频谱利用不足或剥夺。长期演进演进（LTE-A）无线标准规定了固定中继为基站覆盖区域以外的移动用户提供规定的数据吞吐量。在文献中的几种中继传输协议中，最受关注的是带有分布式空时分组码（DSTBC）和多输入多输出（MIMO）的放大转发（AF）协议，因为它能有效地提供合作分集。然而，合作会产生干扰和同步问题，从而降低性能。目标是开发新的和深入的知识，以构建低复杂性，节能，高速，强大的处理器和架构，以处理AF和DSTBC中继网络中的多媒体服务。提出的研究重点是推导新的递归（最优和次优）信号处理算法（基于Jacobi旋转）和架构（基于收缩阵列），用于(i)信道估计，（ii）干扰消除，（iii）收发器优化，（iv）现场可编程门阵列（FPGA）平台上的算法映射，以及(v)软件定义无线电（SDR）算法的实现。信道状态信息（CSI）估计、干扰消除和收发器优化是系统整体性能的关键，也是系统中最繁重的任务。然而，对于无线应用，低复杂性、低功耗、高速和稳定（鲁棒）的架构是非常需要的。为了实现低复杂度和高速的实现，体系结构必须是高度流水线化的，并且在处理数据方面具有并行性。使用雅可比旋转将产生具有固有并行性和计算稳定性的方法。收缩阵列是高度流水线化的并行结构，可以利用基于Jacobi旋转方法的并行性来加快信号处理。对于这种架构的SDR实现，需要在典型的FPGA处理器上映射算法。在这个建议中，我们将推导递归的、最优的信道估计、干扰消除和收发器操作算法。信道估计将在DS进行（不增加RS的负担），并分解为BS-RS和RS-DS链路分量。分解将通过基于Jacobi旋转的非对称复值矩阵奇异值分解（SVD）和Kronecker积来实现。新的信道估计和接收机优化算法将部分使用雅可比旋转和子空间方法推导。现有的和新的算法将在复杂性、速度和功率方面进行优化。这些算法将被优化，以便在特定的FPGA平台上进行映射和有效实现。收缩阵列实现将分析速度和计算强度。