Low-Dimensional-Material-Based Integrated Systems for Energy Storage, Conversion and Delivery

能量存储、传输和转换电路的小型化和片上集成是开启新一代电子应用的关键，从无电池无线传感器到低成本光电子器件。 事实上，仅自供电芯片的生物传感和生物医学意义就令人震惊。 然而，鉴于前端硅CMOS和后端金属的传统几何缩放即将结束，这种电路的小型化仍然是不可能的。 ** 该提案旨在通过使用低维材料（LDM），如一维（1D）碳纳米管（CNT），二维（2D）石墨烯和2D过渡金属二硫族化物（TMD）片来突破缩小缩放回报。直径为1 nF）和电感器（>100 nH）非常大，因此必须位于片外。LDM具有克服这一点的潜力，具有高潜力的纳米结构，包括CNT束/石墨烯螺旋和高密度CNT森林/双层石墨烯/多层石墨烯-h-BN-石墨烯结构。 然而，为了使LDM实现其潜力，必须解决诸如由不良LDM/金属接触引起的不可接受的低品质因数的问题。** 第二个技术挑战是逐步改变有源器件的尺寸和性能。随着传统的Si CMOS缩放越来越受到泄漏和寄生效应的限制，2D TMD由于其薄的主体和合理的带隙而具有高潜力。 然而，目前尚不存在能够捕获足够的器件信息以用于快速电路仿真和芯片设计的紧凑模型，并且许多关键的TMD属性仍然未知（例如，频率相关的噪声特性和传输线性度）。第三个技术挑战是解决可能严重降低高度小型化电路的布局后性能的显著寄生电容。 这可以通过采用“寄生感知”电路设计技术来实现，该技术可以缩小布局前设计和布局后实施之间的差距，并有可能将寄生“浪费”转化为有用的无源元件。**第二阶段：* 一旦解决了实际的基于LDM的无源和有源器件的潜在技术挑战，第二阶段将整合学习并产生电路级模型和设计。 这将包括器件结构和电路拓扑的共同优化，以确保充分利用LDM的独特特性，并针对目标应用优化器件结构。 ** 最终结果将是物理原型，证明LDM实际上可以为无数应用提供能量存储和转换电路。 此外，通过集成全面的有源和无源技术模型库和协同仿真工具，该计划将为未来的特定应用研究奠定基础。

Miniaturization and on-chip integration of energy storage, delivery and conversion circuitry is the key to unlocking a new generation of electronic applications, from battery-less wireless sensors to low-cost photovoltaics. Indeed, the bio-sensing and bio-medical implications of self-powered chips alone are staggering. However, given that conventional geometric scaling of front-end Si CMOS and back-end metals are coming to an end, miniaturization of such circuitry remains will be impossible. **This proposal aims to breakthrough diminishing scaling returns by using low-dimensional materials (LDMs) such as 1-dimensional (1D) carbon nanotubes (CNTs), 2-dimensional (2D) graphene and 2D transition metal di-chalcogenides (TMDs) sheets. With diameter 1 nF) and inductors (>100 nH) are so large that they must be located off-chip. LDMs have potential to overcome this, with high-potential nanostructures including CNT bundles/grapheme spirals and high-density CNT forests/bilayer grapheme/multi-layer graphene-h-BN-graphene structures. However, for LDMs to achieve their potential, problems like the unacceptably low quality factor caused by poor LDM/metal contact must be addressed. **The second technology challenge is to step-change the size and performance of active devices. With conventional Si CMOS scaling increasingly limited by leakage and parasitics, 2D TMDs are high-potential due to their thin body and reasonable bandgap. However, compact models that capture sufficient device information to be used for rapid circuit simulation and chip design do not yet exist, and many key TMD properties are still unknown (e.g. frequency-dependent noise characteristics and transport linearity).**The third technology challenge is to address the significant parasitic capacitances that can severely degrade post-layout performance of highly miniaturized circuits. This can be done by adopting "parasitic-aware" circuit design techniques that close the gap between pre-layout design and post-layout implementation and potentially convert parasitic "waste" into useful passive components.**PHASE II:*Once the underlying technology challenges of practical LDM-based passive and active devices are addressed, Phase II will integrate the learning and produce circuit-level models and designs. This will include co-optimization of device structures and circuit topologies to ensure that the unique properties of LDMs are fully utilized and device structures are optimized for target applications. **The end result will be physical prototypes that prove LDMs can practically miniaturize energy storage and conversion circuitry for a myriad of applications. Furthermore, by integrating a comprehensive library of active and passive technology models and co-simulation tools, this program will be provide a foundation that future application-specific research can build from.