Low-Dimensional-Material-Based Integrated Systems for Energy Storage, Conversion and Delivery

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Miniaturization and on-chip integration of energy storage, delivery and conversion circuitry is the key to unlocking a new generation of electronic applications, from battery-less wireless sensors to low-cost photovoltaics. Indeed, the bio-sensing and bio-medical implications of self-powered chips alone are staggering. However, given that conventional geometric scaling of front-end Si CMOS and back-end metals are coming to an end, miniaturization of such circuitry remains will be impossible. **This proposal aims to breakthrough diminishing scaling returns by using low-dimensional materials (LDMs) such as 1-dimensional (1D) carbon nanotubes (CNTs), 2-dimensional (2D) graphene and 2D transition metal di-chalcogenides (TMDs) sheets. With diameter 1 nF) and inductors (>100 nH) are so large that they must be located off-chip. LDMs have potential to overcome this, with high-potential nanostructures including CNT bundles/grapheme spirals and high-density CNT forests/bilayer grapheme/multi-layer graphene-h-BN-graphene structures. However, for LDMs to achieve their potential, problems like the unacceptably low quality factor caused by poor LDM/metal contact must be addressed. **The second technology challenge is to step-change the size and performance of active devices. With conventional Si CMOS scaling increasingly limited by leakage and parasitics, 2D TMDs are high-potential due to their thin body and reasonable bandgap. However, compact models that capture sufficient device information to be used for rapid circuit simulation and chip design do not yet exist, and many key TMD properties are still unknown (e.g. frequency-dependent noise characteristics and transport linearity).**The third technology challenge is to address the significant parasitic capacitances that can severely degrade post-layout performance of highly miniaturized circuits. This can be done by adopting "parasitic-aware" circuit design techniques that close the gap between pre-layout design and post-layout implementation and potentially convert parasitic "waste" into useful passive components.**PHASE II:*Once the underlying technology challenges of practical LDM-based passive and active devices are addressed, Phase II will integrate the learning and produce circuit-level models and designs. This will include co-optimization of device structures and circuit topologies to ensure that the unique properties of LDMs are fully utilized and device structures are optimized for target applications. **The end result will be physical prototypes that prove LDMs can practically miniaturize energy storage and conversion circuitry for a myriad of applications. Furthermore, by integrating a comprehensive library of active and passive technology models and co-simulation tools, this program will be provide a foundation that future application-specific research can build from.