Code Generation for Specialized Hardware-Supported Functional Units

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Advances in Graphics Processing Units (GPU) started a major trend in the industry towards specialized accelerators. These accelerators were then repurposed for extensive usage in other domains that can benefit from similar hardware architecture design. The effective use of GPUs for the training of Deep Convolution Networks led to the design of Tensor Processing Units (TPUs), also known by different names in offerings by other vendors, which have specific architecture features for matrix operations. This proposal is based on the idea that the functional units originally designed for TPUs can also be repurposed for general-purpose numerical computing and that there might be performance and energy/performance gains in doing so. Thus, the main objectives of the proposed research include: - To investigate the repurposing of functional units originally designed for TPUs for general-purpose high-performance numerical computation. - To study multiple possible configurations of specialized functional units for the execution of numerical-computing loop nests. - To determine which program analysis, and compiler-based code transformations, are necessary to port code written in programming models with, or without, parallel annotations and to make them suitable to benefit from execution in such functional units. - To design profitability functions that can be used to determine which code transformations should be applied to loop nests to make them performant in the functional units and also to enable runtime decisions of when a given computation should be executed in one such functional unit. The proposed research will support the development of solutions that may result in higher performance for scientific and data-analytics applications. The process of developing these solutions will also attempt to leverage emerging automated learning techniques and to integrate them in the code-generation process.