Integrated Optics for High Performance and Energy Efficient Processors

点击翻译按钮获取中文摘要

Context Today, the design of most hardware computing systems, from data centers to edge computing devices, is driven by the need to process massive amounts of data at high rate. The shift to data-centric architectures is needed to allow for the deployment of numerous applications such as autonomous vehicles, decentralized web, cognitive cyber-physical systems, 6G and beyond. This naturally calls for integrated optics technology for fast chip-scale communication and data processing. As silicon photonics is maturing and enables the realization of ever complex devices, new computer organizations are now required to fully take advantage of the technology in very large scale integrated circuits. This leads to the proposed research program which aims at bridging the gap between device designers and computer architecture developers. Objectives The long-term objective of the program is the design of disruptive hardware architectures based on silicon photonics technology. The goal is to improve throughput, latency and energy efficiency of integrated computing systems. To this end, the applicant intends to take advantages of the latest advances in silicon photonics to design architectures capable of processing data during their transmission. Compact and ultra-fast optical accelerators will be designed and embedded in a non-volatile reconfigurable on-chip optical interconnect. The network will be configured by a smart network interface able to pre-calibrate optical devices, which will be evaluated using a scalable and accurate emulation framework. The Research Objectives (RO) are summarized as follow: RO1, short-term: framework to design and emulate silicon photonics-based architectures. The framework will take advantage of Field Programmable Gate Array (FPGA) acceleration for scalable and accurate evaluation of the silicon photonics-based architectures. RO2, short-term: smart optical network interface. In order to reduce communication latency, a network interface capable of anticipating communication according to real-time chip activity will be developed. The interface will involve embedded learning techniques to calibrate the optical devices. RO3, mid-term: toward disruptive computer architectures. The goal is to place silicon photonics at center stage of computing architectures in order to make full use of the technology for high speed processing and data transfer. Optical hardware accelerators will be integrated in the interconnects to reduce the number of Electro-Optic and Opto-Electronic (EO/OE) converters. Impact Canadian companies developing optical components and circuits will be benefitted directly from the cross-disciplinary nature of the program to design optical accelerators for data intensive applications. Companies developing embedded computing systems may use the developed solutions to increase the performance of hardware architectures.