集成电路是体现国家核心竞争力的战略高科技，而超低功耗和抗辐射集成电路更是与国家核心安全息息相关。根据2014年国际固态电路会议（ISSCC）和核与空间辐射效应会议（NSREC）相关报告，随着工艺缩减到65nm和40nm，超低功耗SRAM和抗辐射SRAM设计面临诸多难题，诸多关键技术亟待攻克。本课题正是基于ISSCC和NSREC最新技术趋势：1）深入研究超低功耗SRAM在极端工艺拐角、超低电压和极高温度下的失效机理及高可靠设计技术，创新各关键电路结构，实现SRAM在VDDmin低于400mV下宽温范围内稳定可靠运行；2）深入研究抗辐射SRAM阱隔离结构、阱接触结构、数据存储模式和辐射粒子种类等对单粒子多单元翻转的影响机理及加固设计技术，创新各关键电路结构，实现SRAM在15MeV.cm2/mg粒子辐射下翻转免疫。相关研究有望取得多个原创性研究成果，对提升我国核心集成电路设计水平具有重要意义。

Integrated circuits (ICs), as the strategic high-tech, embody national core competitiveness, extremely ultra-low-power and radiation-hardened ICs are closely related to the national core security. With the technologies shrink to 65nm and 40nm, according to the reports of International Solid State Circuits Conference (ISSCC) and International Nuclear and Space Radiation Effects Conference (NSREC) in 2014, ultra-low-power SRAM and radiation-hardened SRAM are confronted with many design difficulties, many key design techniques need to be resolved. Based on ISSCC and NSREC latest technique trends, this subject will discuss these topics: 1) based on the in-depth study of the failure mechanisms of ultra-low-power SRAM in extreme process corner, very-low voltage and very-high temperature, the high reliability design techniques are proposed, the key circuit structures of SRAM are innovated, and SRAM within stable and reliable work in VDDmin below 400mV and wide temperature range is designed; 2) based on the further study of the effects of well isolation structure, well contact structure, data storage model and single particle type on the radiation mechanism of multiple cell upset, the radiation hardened techniques are proposed, the key circuit structures of radiation hardened SRAM are innovated, and the realization of SRAM in 15MeV.cm2/mg particle radiation is immune for soft error. Related research is expected to obtain a plurality of original research results and has important significance for improving our core IC design capability.