我国航天技术的飞速发展对抗辐射电子元器件的性能提出了更高需求，抗辐射高速数据接口的水平已成为制约我国航天电子元器件性能提升的瓶颈。为支撑新一代高速数据传输（即PCIe4.0）协议，需要攻克16Gbps SerDes抗单粒子辐射加固技术，这将是成功研制新一代高性能航天电子元器件的核心关键。本课题将面向28nm体硅CMOS工艺，深入研究并攻克：1）高精度带隙基准、8GHz高频锁相环、时钟数据恢复电路、连续时间线性均衡器和判决反馈均衡器等模拟电路的SET加固技术；2）高速多时钟域时钟网络、串并转换电路和并串转换电路等数字电路的SET/SEU加固技术；3）全SerDes芯片系统级和版图级的SET/SEU/SEL加固技术。基此将进一步构建16Gbps SerDes抗辐射加固技术平台，相关研究有望在多个方面取得原创性的研究成果，对研制新一代更高数据处理和传输能力的宇航用核心电子元器件具有重要价值。

The rapid development of space technology has put forward higher requirements for the performance of radiation hardened electronic components in China. The level of radiation hardened high-speed data interface has become a bottleneck restricting the performance of space electronic components. In order to support the new generation of high-speed data transmission (PCIe4.0) protocol, radiation hardened 16Gbps SerDes is essential. This project will focus on 28 nm bulk silicon CMOS technology, and research and overcome: 1) SET hardening techniques for analog circuits such as high-precision bandgap reference, 8GHz high-frequency phase-locked loop, clock data recovery circuit, continuous-time linear equalizer and decision feedback equalizer; 2) SET/SEU hardening techniques for digital circuits such as high-speed multi-clock domain clock network, series-to-parallel converter circuit and parallel-to-series converter circuit; 3) SET/SEU/SEL hardening techniques at system level and layout level for whole SerDes chip. On this basis, a radiation hardened by design platform for 16Gbps SerDes is constructed. The related research is expected to achieve original research results in many aspects. It is of great value to develop a new generation of core aerospace electronic components with higher data processing and transmission capabilities.