CdZnTe像素阵列探测器是近年来发展起来的最有前途的室温半导体核辐射探测器，大阵列高分辨率面阵探测器代表了该技术的最新发展方向。随着像元尺寸的减小，高分辨率CZT像素阵列探测器的实现需要解决载流子扩散、载流子俘获、载流子屏蔽和信号串扰等一系列理论问题和技术挑战。本项目提出根据半导体的光电效应、载流子输运和电荷收集理论，建立更精确的大阵列（64×64以上）像素探测器的物理模型，寻求实现高能量分辨率和高空间分辨率的技术途径。在探测器结构参数优化的基础上，提出创新的二维格栅电极设计，不仅提高了电荷收集效率，而且可实现信号的差分输入，大大降低噪声和信号串扰。基于通用集成电路芯片研制具有能谱分辨的光子计数型读出电路，模拟部分采用低噪声、高增益和宽带宽运算放大器，而数字部分则采用高性能FPGA芯片。

CdZnTe pixellated detectors, developed in the present decade, are the most promised room-temperature semiconductor nuclear detectors, and high resolution large array detectors represent the state-of-the-art progress. With the reduction of the pixel size, the realization of high resolution CZT pixellated detectors has to solve theoretical problems and technique challenges such as carrier diffusion, carrier capturing, carrier screening and signal crosstalking. Physical moldel with higher precision for large array (up to 64×64) pixellated detectors is proposed based on opto-electronic effect, carrier transportation and charge collection theories of semiconductors, so that the technologies aimed to high energy resolution and high space resolution can be explored. Besides the parameter optimization of detector structures, a novel 2D grating electrode design is proposed, which not only enhancing the charge collection efficiency, but also achieving diferential input, thus significantly decrease the noise and crosstalk. The read-out circuit for photon counting with spectral resolution will be developed with general purposed IC chip, in which the analog module will employing low noise, high gain, and wide bandwith operational amplifiers, and the digital module will employing high performance FPGA chips.