在纳米集成电路中，每平方厘米能容纳1京个纳米器件，其生产工艺极易引入大量缺陷。在如此大规模、高缺陷率、多缺陷类型的情况下，如何正确实现电路映射，是纳米集成电路发展亟待解决的难题之一。针对这一问题，纳米电路容错映射正成为一个重要的研究方向。本项目将从容错映射方法、容错性能提高与缺陷密度、纳米阵列规模与成品率等三个方面对纳米电路中容错映射问题开展研究。主要研究内容包括：建立非规则纳米阵列结构模型、缺陷注入模型，发展容错映射算法；研究电路等效变换与可映射性、容错性能间的关系，提出高容错能力的电路等效变换算法；研究缺陷密度、纳米阵列规模与成品率间关系；建立实验验证平台验证所提出方法的有效性。项目研究成果，不仅能促进纳米混合集成电路实用化进程，而且为提高我国后CMOS时代集成电路技术的国际竞争力奠定理论基础。

Nanoscale integrated circuit can contain 1 giga nano devices per centimeter square and significant defects are easily introduced in its production process. Under such a huge scale, high defect rate and many defect types, it is one of hard problems how to correctly implement circuit mapping. Against this problem, defect tolerant mapping technology is becoming one of the important research fields. This project will study three aspects of nanoscale integrated circuits in terms of defect tolerant mapping method, defect tolerant performance improvement & defect density, nano array scale & yield. The main research includes: structure models targeting non-regular nano array will be built and defect tolerance algorithms will be developed; the relationship among circuit equivalent conversion, the ability to be mapping and the ability of defect tolerance will be studied and the equivalent circuit conversion algorithm to promote the defect tolerant ability will be presented; the relationship among defect density, nano-array scale and yield will be investigated; experimental platform will be built to verify the effectiveness of presented methods. By studying this project, it can not only speed up the process of nanoscale integrated circuits practical applications, but also lay the theoretical foundation to promote international competitive strength in China for post-CMOS era integrated circuit technology.