高质量单轴压应力GOI纳米线的研究

压应力绝缘膜上的锗薄膜（GOI: Ge-On-Insulator）不仅具有绝缘膜上的硅薄膜（SOI: Si-On-Insulator）结构的优势（低寄生电容、低漏电流等），还具有较高的空穴迁移率，从而被认为未来最有希望的高速/低功耗高性能极大规模集成电路p-MOSFET器件的沟道材料之一。为了实现高性能GOI p-MOSFET器件，制备高质量压应力GOI薄膜是最为关键的因素。本项目拟利用微纳加工技术并采用多步Ge浓缩法解决传统的Ge浓缩法制备GOI薄膜过程中发生的非弹性压应力弛豫以及应力弛豫导致的大量晶体结构缺陷等问题，制备出具有纳米线结构的高质量单轴压应力GOI薄膜，即GOI纳米线，并且系统地从GOI纳米线的制备工艺条件、应力弛豫、晶体结构及其p-MOSFET器件的制备和性能等方面进行深入详细的研究，以获得具有高空穴迁移率增强的高性能GOI纳米线p-MOSFET器件。

Compressive-strained Ge-On-Insulator (GOI) has been considered as one of the most promising p-MOSFET channel material of future high-speed and low-power-consumption ultralarge scale integration (ULSI) because of its high hole mobility and the structure advantage of the Si-On-Insulator (SOI): low parasitic capacitance and leak current. In order to obtain high-performance GOI p-MOSFET devices, the most important factors is the fabrication of high-quality compressive-strained GOI films. This project proposes that a combination of micro/nano fabrication and multi-step Ge condensation effectively suppresses the inelastic-strain relaxation and an anmount of relaxation-induced structure defects during traditional Ge condensation for GOI fabrication, and consequently fabricates high-quality compressive-strain GOI films with a nanowire structure, i.e. GOI nanowire. A systematic study including the fabrication process, strain relaxation, crystal quality of GOI nanowire, and its p-MOSFET devices will be carried out in this project, from which it is expected to obtain high-performance GOI p-MOSFET devices with high-mobility enhancement.