Thermal-Aware Design and Simulation Approach for Optical NoCs

Thermal-Aware Design and Simulation Approach for Optical NoCs
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光学 NoC 的热感知设计和仿真方法

DOI:
10.1109/tcad.2019.2935407
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发表时间:
2020-10
影响因子:
2.9
通讯作者:
Liu Weichen
Liu Weichen
中科院分区:
计算机科学3区
文献类型:
--
作者:
Ye Yaoyao;Zhang Wenfei;Liu Weichen

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对于片上多处理器,一个主要的挑战是如何弥补处理器之间不断增长的速度差距和片上互连延迟。通过在片上网络(NoC)架构中集成光互连,光NoC可以克服传统电片上网络的功率和带宽瓶颈。然而,虽然考虑到在光学NoC中使用的硅光子器件的热敏感性,但是与它们的电对应物相比,光学互连在功率效率方面可能不具有优势。为了解决这个问题,在这篇文章中,我们提出了一个热感知的设计和模拟方法的光学NoCs。关键技术包括从器件级到网络级的热敏感光功率损耗模型、热感知自适应路由机制和热感知仿真平台。热感知仿真平台支持光学NoC仿真、片上温度仿真以及光学热效应建模。利用所提出的热感知仿真平台,我们对一个基于8 × 8$网格的光片上网络在一组合成流量模式下以及典型温度场景下的真实的应用进行了案例研究.通过对不同温度分布的比较分析,得出对于热点分散的芯片温度分布,该方法可以达到更好的优化效果。
For chip multiprocessors, one major challenge is to bridge the increasing speed gap between processor and the global on-chip interconnect delay. By integrating optical interconnects in network-on-chip (NoC) architectures, optical NoCs can overcome the power and bandwidth bottleneck of traditional electrical on-chip networks. However, while considering the thermal sensitivity of silicon photonic devices used in optical NoCs, optical interconnects may not have advantages in power efficiency as compared with their electrical counterparts. To tackle this problem, in this article, we propose a thermal-aware design and simulation approach for optical NoCs. Key techniques include thermal-sensitive optical power loss models from device level to network level, a thermal-aware adaptive routing mechanism, and a thermal-aware simulation platform. The thermal-aware simulation platform enables optical NoC simulation together with on-chip temperature simulation as well as optical thermal effect modeling. With the proposed thermal-aware simulation platform, we conducted a case study of an $8\times 8$ mesh-based optical NoC under a set of synthetic traffic patterns as well as real applications at typical temperature scenarios. By comparing and analyzing different temperature distributions, we can conclude that it can achieves a better optimization effect for the temperature distributions where the hot spots are scattered across the chip.
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