本项目针对吨量级高纯锗探测器暗物质和中微子探测实验对信号动态范围和波形甄别能力等方面提出的新需求，开展低温CMOS前端电路关键技术研究，包括77K低温下MOS晶体管的器件模型搭建、大动态范围和高带宽CMOS前放设计等，并最终研制出低温高纯锗探测器原型前端ASIC芯片，实现200eV–10MeV的信号动态范围、噪声不超过200eV以及前放上升时间不超过5ns等关键技术指标。本项目研制的低温前端芯片是大规模、低本底高纯锗探测器的关键技术之一，对于提高暗物质和中微子探测灵敏度、做出新的物理发现具有重要意义，也将推动高纯锗探测器技术的发展以及在能源和国防领域中的应用。

The project will focus on the development of cryogenic CMOS front-end electronics in order to meet the new stringent requirements for ton-scale HPGe detectors for dark matter search and neutrino-less double beta decay experiments. Several key techniques will be emphasized, including MOS transistor modeling at 77K and design of charge sensitive preamplifier with large dynamic range and high bandwidth. Eventually a highly integrated front-end ASIC for HPGe detectors will be developed with dynamic range from 200eV to 10MeV, noise less than 200eV and rise time less than 5ns. As one of the key technologies for large-scale and low-background HPGe detectors, the cryogenic front-end ASIC is targeting to improve the detection sensitivity by 3 order of magnitude for dark matter and neutrino mass. Besides, it can also be applied for nuclear energy and homeland security applications.