10 nm以下金属/半导体界面结构与电学性能的原位研究

金属与半导体的接触界面对电子器件效率的提高具有重要影响，制造低电阻的集成触点和互连是提高未来超大规模集成电路可靠性关键的一步。纳米尺度下，由于受尺寸效应的影响及实验手段的限制，良好的金属/半导体界面接触的控制变得更加困难。本项目拟采用10 nm以下金属/III-V族纳米线接触作为研究对象，利用球差校正透射电镜和原位性能测量技术，从原子尺度研究10 nm以下金属/III-V族纳米线接触界面在电加载（直流、脉冲等）下的结构演变规律，阐明结构演变机理；探索界面结构对电学性能的影响，建立二者之间的动态关联；最后结合第一性原理计算，分析界面原子排列/晶面取向、界面缺陷、成分分布等对其电学性能的影响机制，研究降低其接触电阻的关键条件。本项目旨在认知电加载对10 nm以下金属/III-V族纳米线接触界面结构、性能的影响并最终实现结构和性能的有效调控，为研发高速及高可靠性的III-V族晶体管提供指导依据。

The contact interface between metal and semiconductor has an important impact on the improvement of the efficiency of electronic devices. Manufacturing low-resistance integrated contacts and interconnections is a key step to improve the reliability of future ultra-large-scale integrated circuits. At the nanometer scale, it is more difficult to control good metal/semiconductor interface contacts due to the size effect and the limitations of experimental methods. In this proposal, through a combination of aberration corrected transmission electron microscope and in-situ measurement technique, we plan to investigate the structural evolution and mechanism of sub-10 nm metal/III-V nanowire contact under diverse electrical loadings (DC, pulse, etc.). And, the influence of interface structure on electrical properties is also to be studied, to establish a dynamic relationship between interfacial atomic structures and electrical properties. Finally, combined with first-principles calculations to analyze the effect of interface atoms arrangement/crystal plane orientation, interface defects, composition distribution, etc. on its electrical properties to reveal the key conditions for reducing its contact resistance. This project aims to understand the impact of electrical loading on the structure and performance of sub-10 nm metal/III-V nanowire contact and ultimately achieve effective control of the structure and performance, providing guidance to develop high-speed and high-reliability III-V transistors.