SiC MOSFET是最重要的功率开关器件之一，是实现高效SiC功率模块与系统应用的关键；SiC MOS栅介质的体电荷陷阱与栅介质/沟道的高界面电荷陷阱密度是限制沟道载流子传输和影响器件可靠性的主要因素。如何实现高质量的栅介质以及低电荷陷阱密度的界面是SiC MOSFET器件开发的核心。本项目将R.D.Shannon的有效离子半径理论引入到栅介质及界面层配位构造上，围绕铝基栅介质配位增强机理和低电荷陷阱密度的界面构造机理进行研究。通过组分调整、结构设计、热力学计算等方法结合工艺优化，实现低体电荷缺陷密度、高可靠性的栅介质，另一方面通过BeO掺杂、界面缺陷及微观结构表征等方法，构造低配位的AlBexOy界面层，实现低缺陷密度的界面，为SiC-MOS 技术中所遇到的缺乏高质量的栅介质、界面陷阱电荷密度过大、理论支撑不足等科学问题提供技术和理论解决方案。

SiC MOSFET is one of the most important power switching devices, and it is the key component for high efficient power module and power system application. The high density of bulk dielectric traps and dielectric/channel interface traps is the dominant factor limiting channel carrier transportation and causing device reliability problem. Realizing the dielectric with high quality as well as the interface with low trap density are the keys for SiC MOSFET device development. In this project, the effective ionic radii theory developed by R. D. Shannon has been introduced to the coordination construction of dielectric and interfacial layer. Investigation has been carried out by focusing on the mechanism of dielectric enhancement and low trap density interface modification. On the one hand, we plan to realize the high-k dielectric for SiC with low bulk trap density and good reliability by changing its composition, designing its structure and performing theoretical calculation. On the other hand, in order to obtain an interface with low defects density, this project would mix BeO with Al2O3, to build for AlBexOy interfacial layer with low coordination number. For SiC-MOS technology, several problems have to be solved, such as no high quality gate dielectric, large interface state density, lacking of supporting theory. Towards these problems, the purpose of this project is to provide technical and theoretical solutions for them.