为克服现有方法存在的过于理想的单故障环境假设及难以同时兼顾定位精度与计算复杂性的不足，基于Memetic框架，本项目拟提出一种面向门级电路拓扑结构的敏感性单元定位方法。为使该方法在保证有较高定位精度的同时仍有较快的求解速度，首先基于信息迁移机制实现电路网表的合理解析与快速分解，再结合启发式规则与图论算法理论给出Memetic算法优质初始解的生成方法；接着基于拟构建的概率信号与迭代策略设计一种面向输入向量的精确快速电路敏感性计算方法以评价个体的敏感性；又结合动量技术和融合了全局进化策略与局部启发式策略的混合优化机制，提出一种快速有效的电路单元敏感性计算方法；然后借助随机概率理论，构建一种基于均匀非伯努利序列的输入向量生成方法以减少准确定位所需的样本规模；最后基于公平原则，设计一种面向电路单元的有效综合敏感性排序方法。通过该研究，以期实现电路结构中敏感性单元的快速有效定位。

To overcome the shortcomings of the existing approaches with an ideal assumption of single fault environment, and an incompatibility between localization accuracy and computational complexity, a gate-level circuit topology structure oriented localization method for reliability-critical gates with the framework of memetic is proposed in this project. In order to ensure higher localization accuracy and fast calculating speed, the following works are performed. Firstly, the information migration mechanism is applied to reasonably parse and quickly decompose the circuit so that each sub-circuit only contains one primary output; then a generation strategy for a high-quality initial solution of the memetic algorithm is given by combining heuristic rules with graph theory algorithms. Secondly, based on the probabilistic signal and iterative strategy to be constructed, an accurate and fast circuit sensitivity estimation model oriented to input vectors is designed to evaluate the individual sensitivity. Thirdly, combining the momentum technology and the hybrid optimization mechanism based on global evolution strategy and local heuristic strategy, a fast and effective sensitivity calculation method for circuit reliability-critical gates is constructed. Then, with the help of stochastic probability theory, a generation method for circuit input vectors based on uniform non-Bernoulli sequence is proposed to reduce the size of data samples required for accurate localization. Finally, based on the principle of fairness, an effective synthetic sensitivity ranking method for reliability-critical gates is designed to identify the gates in descending order with criticality. Through this study, we try to implement the fast and effective localization method for reliability-critical gates in gate-level circuits.