随着集成电路产业的迅速发展，可靠性与容错技术已经成为芯片领域的重要问题之一。现今容错技术的探索依赖于在芯片仿真阶段的大规模统计错误注入实验，然而基于该类实验的可靠性分析有三点缺陷：第一，缺乏对错误产生机制的模拟；第二，缺乏对错误在芯片中传输机制的分析；第三，注错实验通常建立于寄存器传输级及其以下级别，无法快速对错误在高级别的影响进行估计。为解决上述问题，本项目首先通过分析纳米级别芯片中延时错误的产生机制，运用动态时序分析技术进行有物理依据的延时错误注入实验。其次，本项目通过研究芯片中逻辑单元的湮没效应对错误的传输进行动态追踪，从而减少统计注错实验的巨大成本。其三，本项目将错误建立与传输分析集成于高级别处理器设计流程，从而在芯片仿真阶段进行快速故障预测。本项目的意义在于建立一套在芯片高层次设计阶段进行准确可靠性分析的机制，从而辅助设计人员探索针对体系结构及应用程序的容错技术。

Within the era of nanoscale semiconductor technology, reliability has become one serious concern for the design of integrated circuits. Currently, the exploration of fault tolerance techniques to improve the reliability of the microprocessor relies on the large-scale simulated error injection experiment, which lacks the detailed investigation of errors’ physical origin. Furthermore, such experiment incurs significant setup cost and timing efforts, which prohibit its usage for fast evaluation of the errors’ impacts. This project focuses on the modeling and impacts analysis of the timing error, which has become a prevalent type of error for the microprocessor in nanoscale CMOS technology. The errors are extracted from the dynamic timing analysis of post-layout circuit netlist and realized as probabilistic value change of the sequential logic. Afterward, the potential errors in the circuits are accurately traced by incorporating the masking abilities and dynamic behaviors of logic units during the instruction-set simulation of the microprocessor. The proposed analysis of error propagation analytically predicts the impacts of the errors, therefore significantly reduces the cost of large-scale error injection experiment. The framework of error modeling and propagation analysis is integrated into a high-level processor design environment, which facilitates the fast prototyping of architecture and application-level error tolerance techniques.