Research Initiation: Graph Abstractions for Concurrent Processing

具有动态进程间拓扑结构的并发系统提出了一种新的 计算机编程中的控制问题。 目前，程序员 被迫描述拓扑结构的水平类似于 指针或后藤语句。 研究者建议使用 一种基于图形语法的技术， 高层次抽象的方式。 我们系统中的计算代理通过一组 口岸 每个端口都连接到一组其他代理。 的曲线图 语法用于指定法律的拓扑的类，这些拓扑可以是 通过使用语法中的产生式重写而改变。 这可能 更改代理的连接。 一个高层次的选拔机制， 用于使代理能够选择连接到 特定的通信端口。 代理由一组 方法;当收到消息时， 处理该消息被调用。 这项资助下的研究涉及对语言的调查 图形所需的功能和编程环境支持- 基于语法的并发编程方法， 该系统在共享内存和消息传递架构上，以及 逻辑图映射算法的研究 物理处理器拓扑。

Concurrent systems with dynamic interprocess topology present a new control problem in computer programming. Currently programmers are forced to describe topologies at a level analogous to that of the pointer or the goto statement. The investigator proposes the use of a technology based on graph grammars to control interconnections in a high-level, abstract manner. The computational agents in our system communicate through sets of ports. Each port is connected to a set of other agents. A graph grammar is used to specify the class of legal topologies, which may be altered by rewriting using a production in the grammar. This may change the connectivity of agents. A high-level selection mechanism is employed to enable an agent to select subsets of agents connected to particular ports for communication. Agents consist of a set of methods; when a message is received the appropriate method for processing that message is invoked. The research under this grant involves the investigation of language features and programming environment support necessary for a graph- grammar based approach to concurrent programming, the implementation of the system both on shared-memory and message-passing architectures, and the investigation of algorithms for the mapping of logical graph topologies onto physical processor topologies.