RIA: System-Level Partitioning of VLSI Circuits Using DesignEvaluators

本文研究的是系统级分区的自动化问题。特别是，它解决了划分设计以最小化VLSI芯片数量的任务，同时仍满足对系统性能和芯片参数的限制。P.I.正在推广一个标准单元芯片的面积估计模型，以处理其他布局设计风格。该模型通过提供对设计布局区域的准确估计，在开发系统级分区工具方面发挥了核心作用。正在开发评估该设计的其他方面和优点的免费工具，如功耗、性能和管脚数量。这些工具正被集成到一个类似电子表格的设计辅助工具中，使设计人员能够与系统进行交互。本研究探讨设计的系统层级划分，以针对多个参数来优化系统设计。P.I.有新的想法，在解决这个复杂的问题上显示出了希望。首席研究员是一位有前途的、有能力的年轻教授，他应该对这一领域做出重大贡献。

This research is on automation of the system level partitioning problem. In particular it addresses the task of partitioning a design so as to minimize the number of VLSI chips, while still satisfying constraints on system performance and chip parameters. The P.I. is generalizing a model for area estimation for standard cell chips to handle other layout design styles. This model plays a central role in developing system level partitioning tools by providing accurate estimates of the design layout areas. Complimentary tools which evaluate other aspects and merits of the design, such as power consumption, performance and pin count are being developed. The tools are being integrated into a spreadsheet-like design aid which will allow the designer to interact with the system. This research investigates system level partitioning of a design so as to optimize system design with respect to many parameters. The P.I. has novel ideas, which show promise in solving this complex problem. The principal investigator is a promising and competent young professor who should make significant contributions to the field.