Very Large-Scale Integration High Throughput Rate Architectures for Systolic Array Processors

这项研究工作的主要目标是开发一个预- 高吞吐量VLSI脉动阵列的制造工程模型 基于最小二乘QR的处理芯片（或芯片组） 分解算法 这种芯片是为通用 脉动卡尔曼滤波应用。 一个直接的应用是 提高目前可实现的跟踪精度和吞吐量， 商用全球定位系统（GPS）接收器。 在第一阶段， 开发脉动阵列LS架构的可行性， 已经成功地演示了吞吐率信号处理器。 第二阶段的脉动阵列设计是基于修改后的快速 第一阶段开发的Givens算法。 基于故障的新算法- 第一阶段确定的宽容方法得到进一步发展，包括 故障识别与自动重构 QR脉动阵列的并行处理特性。 预制芯片模型的开发需要确定 以下用于脉动处理器的VLSI设计技术： 算法到体系结构的依赖图映射， 从大规模问题到固定规模体系结构; 和I/O线;以及数据流和计算的软件模拟。 第二阶段的研究工作开发了可以 扩展到一般VLSI脉动LS处理器，从而允许容易 该技术未来的商业化应用于其他信号处理 应用.

The major objective of this research effort is to develop a pre- fabrication engineering model of a high throughput VLSI systolic array processing chip (or chip set) based on least-square (LS) QR decomposition algorithm. This chip is being developed for general systolic Kalman filtering applications. An immediate application is to improve the tracing accuracies and throughput currently achievable in commercial Global Position Systems (GPS) receivers. In Phase I, the feasibility of developing systolic array LS architectures for high throughput rate signal processors has been successfully demonstrated. The systolic array design in Phase II is based on the modified Fast Givens algorithm developed in Phase I. The novel algorithm-based fault- tolerant approach identified in Phase I is further developed to include fault-identification and automatic reconfiguration based on inherent parallel processing characteristics of the QR systolic arrays. Development of the pre-fabrication chip model requires determination of the following VLSI design technologies for systolic processors: dependence graph mapping of algorithms to architecture, partitioning of large size problems to fixed size architecture; tradeoffs on internal and I/O lines; and software simulation of data flow and computations. This Phase II research effort develops methodologies which can be extended to general VLSI systolic LS processors and thus allow easy future commercialization of this technology to other signal processing applications.