Presidential Young Investigators Award: mm-Wave Devices and Integration Techniques

减小有源器件电容可以提高电子器件的固有响应时间。当器件使用复杂的光刻工具（如电子束光刻）横向缩放时，器件也必须垂直缩放以确保适当的电荷控制。这包括FET和HEMT等器件中有源通道和接触区域的细化。特别是接触区域，很难通过传统的技术，如离子注入来扩展。选择性蚀回和再生技术将极大地影响具有减少短沟道效应的纳米栅极长度器件的发展。使用化学辅助离子束蚀刻系统和再生室将允许制造具有减少短通道效应的纳米栅极长度器件。垂直器件是激励的，因为在横向器件中没有引起短通道效应的基片电流增强。此外，关键器件尺寸通过外延技术增长，因此可以做得非常小，从而减少电子传递时间并提高器件速度。这些和其他先进的制造技术将被研究用于生产集成电路应用的性能改进的固态器件。

The inherent response time of electronic devices can be improved by decreasing the active device capacitance. As devices are scaled laterally using sophisticated lithographic tools, such as e-beam lithography, the devices must also be scaled vertically to ensure proper charge control. This includes the thinning of active channel and contact regions in devices such as FET's and HEMT's. Contact regions, in particular, are difficult to scale by conventional techniques such as ion-implantation. Selective etch-back and regrowth techniques will substantially influence the development of nanometer gate length devices with reduced short channel effects. Using a chemically assisted ion-beam etching system and a regrowth chamber will allow nanometer gate length devices with reduced short channel effects to be fabricated. Vertical devices are exciting because enhanced substrate currents which cause short channel effects in lateral devices are absent. Also, the critical device dimensions are grown by epitaxial techniques and hence can be made extremely small, thereby decreasing electron transit times and enhancing device speed. These and other advanced fabrication techniques will be investigated for use in producing improved performance solid state devices for integrated circuit applications.