RIA: Fault Tolerance in Analog VLSI Focal Plane Processors

Andreou 模拟超大规模集成电路是一种很有前途的方法来设计系统的机器视觉，因为它导致分布式，数据驱动的架构，直接映射的光刺激到计算硬件的关键，硅基板。 这类新兴的信号处理系统是基于相对简单的计算原语，如对数光电探测器，聚合电阻网络和耦合非线性电阻网络。 此外，还有功率和面积有效的功能，使它们对晶圆级集成有吸引力。 然而，这种系统在晶圆级的制造将强烈依赖于建立设计方法，使它们在制造过程中的缺陷鲁棒。 同样重要的是，这些必须与产量估计模型以及测试和故障分析程序相结合。 上述问题在本研究中得到解决，在一个全面的计划，涉及分析计算和实验研究。

Andreou Analog VLSI is a promising approach to the design of systems for machine vision since it leads to distributed, data driven architectures, that map the light stimuli directly to the crux of computing hardware, the silicon substrate. This emerging class of signal processing systems is based on relatively simple computational primitives such as logarithmic photodetectors, aggregating resistive networks and coupled non-linear resistive networks. Furthermore, there are power and area efficient features that make them attractive for wafer scale integration. However, manufacturing of such systems at the wafer scale will strongly depend on establishing design methodologies that make them robust to defects in the fabrication process. Equally important, these must be augmented with yield estimation models as well as testing and failure analysis procedures. The above issues are addressed in this research in a comprehensive program that involves both analytical calculations and experimental studies.