RIA: Parallel, Mixed-Level Simulation of Digital Systems

本研究是关于利用通用并行处理器加速混合级模拟的研究。一个现有的并行模拟器正在开发中，以使代码更易于移植，并可供其他人在几台并行机器上使用。正在使用并行离散事件仿真。讨论的主题是：(1)寻找改进大型扇出电路节点的模拟的技术；以及(2)开发图形处理算法以改进分区、改善信号分布和进行异步消息传递。使用模拟器对基准设计进行实验，以研究划分、组件迁移、任务大小以及计算和通信开销的影响。

This research is on accelerating mixed level simulation using general purpose parallel processors. An existing parallel simulator is being developed to make the code more portable and available for others to use on several parallel machines. Parallel discrete event simulation is being used. Topics addressed are: (1) finding techniques for improving the simulation of large fan- out circuit nodes; and (2) developing graph manipulation algorithms to improve partitioning, to improve signal distribution, and to do asynchronous message passing. Experiments on benchmark designs with the simulator to study the effects of partitioning, component migration, task size, and computational and communication overhead are being conducted.