Towards Automatic Synthesis of Behavioral VHDL

这是一项针对女科学家和女工程师的研究计划补助金。正在计划一项研究计划，从一个非常高级的体系结构规范中自动综合VHDL语言。方法是将最先进的软件综合技术过渡到CAD设计自动化。目前正在对几个独立于实现的高级体系结构规范模型进行可行性研究。其他活动包括：定义一组VHDL语言软件综合操作符，开发纯行为级体系结构规范的表示，以及执行这些规范的可行性测试。

This is a Research Planning Grant for Women Scientists and Engineers. A research program in automating the synthesis of the VHDL language from a very high-level architectural specification is being planned. The approach is to transition state-of-the-art software synthesis technology to CAD design automation. A feasibility study of several high-level architectural specification models, which are implementation independent, is being conducted. Other activities are: defining a set of VHDL software synthesis operators, developing representations of pure behavioral level architectural specifications, and performing feasibility tests of these specifications.