Automatic FPGA Interconnect Synthesis and Understanding FPGA Architecture

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The fast pace of technological advancement in recent years has been driven by the ability to fabricate digital chips with ever-increasing capability. Each new generation of chip fabrication technology uses smaller transistors and provides exponential improvements in computing capacity. It is less well known that the sophistication and investment required to design and build those chips has *also* been increasing at a near-exponential rate, threatening this progress in the future. Fortunately, the rise of pre-fabricated, user-programmable chips, known as Field-Programmable Gate Arrays (FPGAs), make it possible to use this fantastic technology with far less risk and sophistication. Indeed, the vast majority of all digital hardware design work is done using FPGAs; only in the very high volume systems (such as those in computers and mobile devices) are custom-built chips are used. Everywhere else, some form of programmable device is used - either a computer processor of some kind or an FPGA. There are two key barriers to the wider use and adoption of FPGAs that we address in this research: First, advantages of pre-fabricated FPGA-based hardware must be compared to the other kind of pre-fabricated but programmable digital chips: computers, which are programmed with software. It is much easier to create software than hardware and there many more people capable of writing software. There has long been an effort in research and industry to make the creation of hardware easier, but many of these efforts trade that ease for quality of result. However, it is that performance and energy-efficiency of hardware that are its key advantages over software running on processor. Our goal in this research is to find other ways of making the hardware design process easier, without losing the quality of the result. One of the hardest things to do in the design process is the design of interconnection between hardware computational units. Each such link must be built appropriate to the performance needs of the computation. We propose to build, in stages, a tool that helps the designer more automatically create and vary that interconnect in the face of specific performance requirements. Our ultimate goal is to automatically optimize the interconnect design, and thus release the designer from the burden of re-implementing it many times. With this capability, we believe it will make the designer's job much easier, and enable high-level tools to more successfully help with other parts of the design process. The second barrier to the wider adoption of FPGAs is the cost of the flexibility required to make a pre-fabricated device usefully programmable. The cost can be prohibitive in high volume applications: simple programmable logic is ten to thirty times the cost of non-programmable logic, as our group has reported in a widely-cited paper. The second thrust of this research proposal is to explore a fundamentally new way of synthesizing circuits into FPGAs, as a way to more deeply understand the minimum amount of flexibility actually required. We plan to do this by building a synthesis approach that combines many of the previously-separated steps that are used to take an engineer's design and put it into the FPGA. At the same time, we will carefully vary the amount of flexibility available, reducing it from its current amount. Our goal is to gain insight into ways to reduce flexibility and therefore cost. Finally, our research group is well-known for the only open-source synthesis tool chain for FPGAs, used throughout the world in FPGA architecture and CAD research and startups. We plan to continue to improve the capabilities and sophistication of this software.