PYI: CAD Tools for New Circuit Technologies

掠夺这项研究是为了开发系统级的模拟能力，这些能力与芯片级的模拟能力一样强大。为此，正在开发可应用于集成电路、封装、模块和板级而不损失通用性的工具。正在研究的具体领域包括：牺牲部分精度以提高效率的快速提取技术；以及支持自上而下设计的模拟模型和技术。电路板或多芯片模块的时序分析需要开发用于在系统仿真级别提取、表征和模拟传输线的工具。为此，正在探索类似于片上RC互连电路的互连宏模型，它们与系统级设计自动化工具兼容。

Pillage The research is on developing simulation capabilities at the system level, which are as powerful as those at the chip level. To this end, tools which are applicable at the integrated circuit, packaging, module, and board levels without loss of generality are being developed. Specific areas being investigated are: fast extraction techniques which trade off some accuracy for efficiency; and simulation models and techniques to enable topdown design. Timing analysis of boards or multi-chip modules requires development of tools for the extraction, characterization and simulation of transmission lines at the system simulation level. Toward this end interconnect macro- models, similar to those for on-chip RC interconnect circuits, which are compatible with system-level design automation tools, are being explored.