The U.S.C. Multiprocessor Testbed: A Testbed for Scalable Shared-Memory Systems

Dubois 一个用于在多处理器中试验内存层次结构的测试平台正在得到支持。 测试平台中的处理器节点包含由现场可编程门阵列制成的高速缓存和存储器系统控制器。 为了实验内存控制机制或一致性技术，研究人员对门阵列进行编程以实现该机制。 为了支持实验技术的软件，正在修改GNU-C编译器以生成适当的代码，例如非阻塞预取，并正在移植Mach微内核以提供线程调度。

Dubois A testbed for experimenting with memory hierarchies in multiprocessors is being supported. A processor node in the testbed contains cache and memory system controllers made from field-programmable gate arrays. To experiment with a memory control mechanism or coherency technique, the investigators program the gate arrays to implement the mechanism. For software support of experimental techniques, the GNU-C compiler is being modified to generate appropriate code, such as non-blocking prefetches, and the Mach microkernel is being ported to provide thread scheduling.