VLSI Design-for-Test Laboratory

正在为电气和计算机工程课程开发超大规模集成电路实验室和设计课程。这些课程为学生提供了开发vlsi芯片产品的经验。在这种情况下，学生组成团队，承担整个设计过程：逻辑设计、门级、布图级、仿真/验证、测试生成和测试返回的原型芯片。建议的课程强调集成电路产品质量的重要性，特别是测试。学生在学习设计和测试技术的早期就采用并行工程的概念，并且考虑和解决集成电路制造和批量生产中出现的问题。研究了面向测试的设计（Design- for-test）技术，并由设计团队进行了实际实现，使集成电路芯片产品易于测试。所要求的项目包括一台台式专用集成电路测试仪、逻辑验证和测试生成CAD软件，这是实施“为测试而设计”实验课程所必需的。

A VLSI laboratory and design courses are being developed for the electrical and computer engineering curriculum. These courses provide students with experience in the development of VLSI-chip products. In this setting, students form teams and undertake the whole design process: logic design, gate-level, layout-level, simulation/verification, test generation, and testing of the returned prototype chips. The proposed courses emphasize the importance of quality in the IC products, particularly testing. Students adopt the concept of concurrent engineering early in their studies of the design and testing techniques, and problems that arise in the manufacturing and mass production of the ICs are considered and solved. Design- for-test techniques are studied and their actual implementation, which makes the IC-chip products easy to test, are carried out by the design teams.The items requested comprise a benchtop ASIC tester and logic verification and test generation CAD software, which are essential for the implementation of Design-for-Test laboratory courses.