SHF: Small: Testing and Design-for-Test Techniques for Monolithic 3D Integrated Circuits

SHF：小型：单片 3D 集成电路的测试和测试设计技术

• 批准号: 2309822
• 负责人: Krishnendu Chakrabarty
• 金额: $ 50万
• 依托单位: Arizona State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-01-01 至 2024-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2309822&HistoricalAwards=false
• 关键词: SHF; Small; Testing; Design; Test

Fabrication of high-performance integrated circuits is relying increasingly on three-dimensional (3D) integration based on through-silicon vias (TSVs). However, fabrication constraints restrict the integration density that can be achieved using this technology. A recent innovation called Monolithic 3D (M3D) integration has the potential to achieve higher device density and performance compared to 3D stacking based on TSVs. This project seeks to develop efficient ways to test M3D-based integrated circuits, by targeting testing and 'design-for-test' (DfT) methods. Advances in testing and DfT will enable high reliability and low defective-parts-per million, which will enhance the competitiveness of US semiconductor companies. Synergies between research on testing of M3D and on design tools and fabrication will foster a community of researchers and lead to further advances in M3D integration. High-school students from the North Carolina School of Science and Mathematics will be mentored though projects in this space. The outreach plan includes engagement with the Duke Technology Scholars Program, which targets women undergraduates early in their careers. The anticipated outcomes of this research are methodologies and tools to analyze, model, and screen manufacturing defects, as well as DfT solutions to enable testing, defect isolation, and yield enhancement. Research on testing and DfT for M3D is not only timely, but it is likely to find easy acceptance owing to zero legacy, and can therefore have a dramatic impact on research and industry practice.Specific research goals in this project include the following: (1) A built-in self-test (BIST) solution to detect and diagnose faults in inter-layer vias (ILVs) and the reuse of this BIST infrastructure for detecting faults in logic and memory tiers. (2) Design of BIST controllers for coordinating test application. (3) Test generation for delay faults introduced by device coupling in M3D, and defects in ILVs and the inter-layer dielectric. (4) Design of the power-distribution network to increase resilience to the problems of electromigration and stress migration. Close collaborations are underway with partners at leading companies and internationally renowned institutions in this field. Research findings will be integrated in VLSI design and testing courses at Duke and lecture materials will be made available to the broader community.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

高性能综合电路的制造越来越依赖于基于通过硅VIA（TSV）的三维（3D）集成。但是，制造约束限制了使用该技术可以实现的集成密度。与基于TSV相比，最近一种称为Monolithic 3D（M3D）集成的创新具有实现更高的设备密度和性能的潜力。该项目旨在通过定位测试和“测试”（DFT）方法来开发有效的方法来测试基于M3D的集成电路。测试和DFT的进步将使高度可靠性和较低的零件有缺陷，这将增强美国半导体公司的竞争力。在测试M3D和设计工具和制造方面的研究之间的协同作用将促进研究人员社区，并在M3D集成方面进一步进步。来自北卡罗来纳州科学与数学学院的高中生将在这个领域的项目中得到指导。宣传计划包括与杜克技术学者计划的互动，该计划针对妇女在职业生涯初期的本科生。这项研究的预期结果是分析，建模和屏幕制造缺陷的方法和工具，以及DFT解决方案，以实现测试，缺陷隔离和提高产量。对M3D的测试和DFT的研究不仅及时，而且由于命令零而可能会很容易接受，因此可能会对研究和行业实践产生巨大影响。该项目的特定研究目标包括以下内容：（1）内置的自我测试（BIST）（BIST）检测和诊断（bist）在此范围内（bist）的错误（INFRASE）（ielvs）中的故障（ILVS）中的故障（ILVS），以进行此类错误（ILV）。和内存层。 （2）设计用于协调测试应用程序的BIST控制器的设计。 （3）通过设备耦合在M3D中引入的延迟故障的测试生成，以及ILV和层间介电的缺陷。 （4）设计电源网络的设计，以提高对电气移民和压力迁移问题的弹性。与该领域领先公司和国际知名机构的合作伙伴进行了密切合作。 研究发现将集成到杜克大学的VLSI设计和测试课程中，并将向更广泛的社区提供演讲材料。该奖项反映了NSF的法定任务，并被认为是通过基金会的知识分子优点和更广泛影响的评估标准来通过评估来获得支持的。

项目成果

Transferable Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs

基于可转移图神经网络的单片 3D IC 延迟故障定位

• DOI: 10.1109/tcad.2023.3275532
• 发表时间: 2023
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Hung, Shao-Chun;Banerjee, Sanmitra;Chaudhuri, Arjun;Kim, Jinwoo;Lim, Sung Kyu;Chakrabarty, Krishnendu
• 通讯作者: Chakrabarty, Krishnendu

Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning *

使用强化学习插入测试点，对单片 3D IC 进行电源安全测试 *

• DOI: 10.1109/ets56758.2023.10174135
• 发表时间: 2023
• 期刊: IEEE European Test Symposium
• 作者: Hung, Shao-Chun;Chaudhuri, Arjun;Chakrabarty, Krishnendu
• 通讯作者: Chakrabarty, Krishnendu

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs

• DOI: 10.1109/tvlsi.2022.3228850
• 发表时间: 2023-03
• 期刊: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• 影响因子: 2.8
• 作者: Arjun Chaudhuri;Sanmitra Banerjee;Jinwoo Kim;S. Lim;K. Chakrabarty