SHF: Small: Testing and Design-for-Test Techniques for Monolithic 3D Integrated Circuits

高性能集成电路的制造越来越依赖于基于硅通孔（tsv）的三维（3D）集成。然而，制造限制限制了使用该技术可以实现的集成密度。与基于tsv的3D堆叠相比，最近一项名为单片3D （M3D）集成的创新技术有可能实现更高的设备密度和性能。该项目旨在通过针对测试和“为测试而设计”（DfT）方法，开发有效的方法来测试基于m3d的集成电路。测试和DfT的进步将使高可靠性和低缺品率成为可能，这将提高美国半导体公司的竞争力。M3D测试研究与设计工具和制造研究之间的协同作用将培养一个研究人员社区，并导致M3D集成的进一步发展。来自北卡罗来纳科学与数学学院的高中生将通过这个空间的项目得到指导。拓展计划包括与杜克科技学者项目（Duke Technology Scholars Program）的合作，该项目针对的是职业生涯早期的女性本科生。本研究的预期结果是分析、建模和筛选制造缺陷的方法和工具，以及支持测试、缺陷隔离和提高产量的DfT解决方案。对M3D测试和DfT的研究不仅及时，而且由于零遗留问题，它很容易被接受，因此可以对研究和行业实践产生巨大影响。本项目的具体研究目标包括：(1)内置自检（BIST）解决方案，用于检测和诊断层间通孔（ilv）中的故障，并重用该BIST基础架构来检测逻辑和存储层中的故障。(2)协调测试应用的BIST控制器设计。(3) M3D中器件耦合引入的延迟故障、ilv和层间介质缺陷的测试生成。(4)配电网的设计，以增加对电迁移和应力迁移问题的弹性。我们正在与该领域的领先公司和国际知名机构的合作伙伴进行密切合作。研究成果将被整合到杜克大学的VLSI设计和测试课程中，讲座材料将提供给更广泛的社区。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

Fabrication of high-performance integrated circuits is relying increasingly on three-dimensional (3D) integration based on through-silicon vias (TSVs). However, fabrication constraints restrict the integration density that can be achieved using this technology. A recent innovation called Monolithic 3D (M3D) integration has the potential to achieve higher device density and performance compared to 3D stacking based on TSVs. This project seeks to develop efficient ways to test M3D-based integrated circuits, by targeting testing and 'design-for-test' (DfT) methods. Advances in testing and DfT will enable high reliability and low defective-parts-per million, which will enhance the competitiveness of US semiconductor companies. Synergies between research on testing of M3D and on design tools and fabrication will foster a community of researchers and lead to further advances in M3D integration. High-school students from the North Carolina School of Science and Mathematics will be mentored though projects in this space. The outreach plan includes engagement with the Duke Technology Scholars Program, which targets women undergraduates early in their careers. The anticipated outcomes of this research are methodologies and tools to analyze, model, and screen manufacturing defects, as well as DfT solutions to enable testing, defect isolation, and yield enhancement. Research on testing and DfT for M3D is not only timely, but it is likely to find easy acceptance owing to zero legacy, and can therefore have a dramatic impact on research and industry practice.Specific research goals in this project include the following: (1) A built-in self-test (BIST) solution to detect and diagnose faults in inter-layer vias (ILVs) and the reuse of this BIST infrastructure for detecting faults in logic and memory tiers. (2) Design of BIST controllers for coordinating test application. (3) Test generation for delay faults introduced by device coupling in M3D, and defects in ILVs and the inter-layer dielectric. (4) Design of the power-distribution network to increase resilience to the problems of electromigration and stress migration. Close collaborations are underway with partners at leading companies and internationally renowned institutions in this field. Research findings will be integrated in VLSI design and testing courses at Duke and lecture materials will be made available to the broader community.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.