Architecture and Synthesis Techniques for Embedded Systems
Architecture and Synthesis Techniques for Embedded Systems
批准号:
9501615
负责人:
Rajesh Gupta
金额:
$11.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1995
资助国家:
美国
项目状态:
已结题
起止时间:
1995-05-01 至 1998-04-30
中文摘要
本文研究的是基于微电子技术的“嵌入式系统”的综合技术。嵌入式系统是在严格的时间性能和成本限制下为特定功能而设计的系统。设计自动化技术正在开发中,用于设计人员可以评估各种嵌入式系统架构和设计之间的权衡的框架。该框架的主要功能是:(a)执行延迟和速率约束的时间分析;(b)在时间约束下生成可嵌入软件和运行时系统;(c)软件大小-性能权衡;(d)架构替代方案的性价比分析,例如预取和转发硬件。这项工作正在探索系统划分和转换技术,以构建在优化系统开发成本的同时“保证”约束满足的系统实现。
英文摘要
This research is on synthesis techniques for micro-electronics- based "embedded systems". An embedded system is one designed for a specific functionality under stringent constraints on its timing performance and cost. Design automation techniques are being developed for use in a framework where the designer can assess tradeoffs between various embedded system architectures and designs. The main capabilities of this framework are: (a) timing analysis for both execution delay and rate constraints; (b) embeddable software and runtime system generation under timing constrains; (c) software size-performance tradeoffs; (d) cost- performance analysis of architectural alternatives, such as pre- fetch and forward hardware. This work is exploreing system partitioning and transformation techniques to build system implementations that "guarantee" constraint satisfaction while optimizing system development cost.
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